Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

ID 683492
Date 1/10/2019
Public
Document Table of Contents

2.2.5.1. Using Synthesis Attributes

The Intel® Quartus® Prime software translates synthesis attributes into standard assignments during compilation. These assignments appear in the Pin Planner. Intel® Quartus® Prime synthesis supports the chip_pin, useioff, and altera_attribute synthesis attributes.

If you modify or delete these assignments in the Pin Planner and then recompile your design, the Pin Planner changes override the synthesis attributes.

Use the altera_attribute synthesis attribute to create other pin‑related assignments in your HDL code. The altera_attribute attribute supports all types of instance assignments. The following examples use the altera_attribute attribute to embed Fast Input Register logic option assignments and I/O standard assignments in both a Verilog HDL and a VHDL design file.

altera_attribute Synthesis Attribute in Verilog HDL

input my_pin1 /* synthesis altera_attribute = "-name FAST_INPUT_REGISTER ON; -name IO_STANDARD \"2.5 V\" " */ ;

altera_attribute Synthesis Attribute in VHDL

entity my_entity is
		port(
				my_pin1: in std_logic
		);
end my_entity;
architecture rtl of my_entity is 
begin

attribute altera_attribute : string;
attribute altera_attribute of my_pin1: signal is "-name FAST_INPUT_REGISTER ON;
-- The architecture body 
end rtl;

Use the chip_pin and useioff synthesis attributes to create pin location assignments and to assign Fast Input Register, Fast Output Register, and Fast Output Enable Register logic options. The following examples use the chip_pin and useioff attributes to embed location and Fast Input Register logic option assignments in Verilog HDL and VHDL design files.

useioff and chip_pin Synthesis Attributes in VHDL

entity my_entity is
		port(
					my_pin1: in std_logic
		);
end my_entity;

architecture rtl of my_entity is
attribute useioff : boolean;
attribute useioff of my_pin1 : signal is true;
attribute chip_pin : string;
attribute chip_pin of my_pin1 : signal is "C1";
begin -- The architecture body 
end rtl;

chip_pin Synthesis Attribute in Verilog HDL

input my_pin1 /* synthesis chip_pin = "C1" useioff = 1 */;

Did you find the information on this page useful?

Characters remaining:

Feedback Message