2.1. I/O Planning Overview 2.2. Assigning I/O Pins 2.3. Importing and Exporting I/O Pin Assignments 2.4. Validating Pin Assignments 2.5. Verifying I/O Timing 2.6. Viewing Routing and Timing Delays 2.7. Analyzing Simultaneous Switching Noise 2.8. Scripting API 2.9. Managing Device I/O Pins Revision History
1. Constraining Designs
|Intel® Quartus® Prime Design Suite 18.1|
|This document is part of a collection. You can download the entire collection as a single PDF: Intel® Quartus® Prime Standard Edition User Guides - Combined PDF link|
The design constraints, assignments, and logic options that you specify influence how the Intel® Quartus® Prime Compiler implements your design. The Compiler attempts to synthesize and place logic in a manner than meets your constraints. In addition, design constraints also have an impact on how the Timing Analyzer and the Power Analyzer influence synthesis, placement, and routing.
You can specify design constraints in the GUI, with scripts, or directly in the files that store the constraints. The Intel® Quartus® Prime software preserves the constraints that you specify in the GUI in the following files:
- Intel® Quartus® Prime Settings file (<project_directory>/<revision_name>.qsf)—contains project-wide and instance-level assignments for the current revision of the project, in Tcl syntax. Each revision of a project has a separate .qsf file.
- Synopsys* Design Constraints file (<project_directory>/<revision_name>.sdc)—the Timing Analyzer uses industry-standard Synopsys* Design Constraint format and stores those constraints in .sdc files.
Did you find the information on this page useful?