Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

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ID 683492
Date 1/10/2019
Public
Document Table of Contents
Document Table of Contents x
1. Constraining Designs 2. Managing Device I/O Pins A. Intel® Quartus® Prime Standard Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints Designs in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints Designs in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Intel® Quartus® Prime GUI 1.1.4. Specifying Timing Constraints in the GUI
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify I/O Constraints in Pin Planner 1.1.2.3. Adjust Constraints with the Chip Planner 1.1.2.4. Constraining Designs with the Design Partition Planner
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Intel® Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
1.2.5. Tcl-only Script Flows x
1.2.5.1. Tcl-only Timing Analysis
2. Managing Device I/O Pins x
2.1. I/O Planning Overview 2.2. Assigning I/O Pins 2.3. Importing and Exporting I/O Pin Assignments 2.4. Validating Pin Assignments 2.5. Verifying I/O Timing 2.6. Viewing Routing and Timing Delays 2.7. Analyzing Simultaneous Switching Noise 2.8. Scripting API 2.9. Managing Device I/O Pins Revision History
2.1. I/O Planning Overview x
2.1.1. Basic I/O Planning Flow 2.1.2. Integrating PCB Design Tools 2.1.3. Intel Device Terms
2.2. Assigning I/O Pins x
2.2.1. Assigning to Exclusive Pin Groups 2.2.2. Assigning Slew Rate and Drive Strength 2.2.3. Assigning Differential Pins 2.2.4. Entering Pin Assignments with Tcl Commands 2.2.5. Entering Pin Assignments in HDL Code
2.2.3. Assigning Differential Pins x
2.2.3.1. Overriding I/O Placement Rules on Differential Pins
2.2.5. Entering Pin Assignments in HDL Code x
2.2.5.1. Using Synthesis Attributes 2.2.5.2. Using Low-Level I/O Primitives
2.3. Importing and Exporting I/O Pin Assignments x
2.3.1. Importing and Exporting for PCB Tools 2.3.2. Migrating Assignments to Another Target Device
2.4. Validating Pin Assignments x
2.4.1. I/O Assignment Validation Rules 2.4.2. Checking I/O Pin Assignments in Real-Time 2.4.3. I/O Assignment Analysis 2.4.4. Understanding I/O Analysis Reports
2.4.3. I/O Assignment Analysis x
2.4.3.1. Early I/O Assignment Analysis Without Design Files 2.4.3.2. I/O Assignment Analysis With Design Files 2.4.3.3. Overriding Default I/O Pin Analysis
2.5. Verifying I/O Timing x
2.5.1. Running Advanced I/O Timing 2.5.2. Adjusting I/O Timing and Power with Capacitive Loading
2.5.1. Running Advanced I/O Timing x
2.5.1.1. Board Trace Models 2.5.1.2. Defining the Board Trace Model 2.5.1.3. Modifying the Board Trace Model 2.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 2.5.1.5. Advanced I/O Timing Analysis Reports
2.8. Scripting API x
2.8.1. Generate Mapped Netlist 2.8.2. Reserve Pins 2.8.3. Set Location 2.8.4. Exclusive I/O Group 2.8.5. Slew Rate and Current Strength
1. Constraining Designs
2. Managing Device I/O Pins
A. Intel® Quartus® Prime Standard Edition User Guides

1.4. Constraining Designs Revision History

Document Version Intel® Quartus® Prime Version Changes
2019.01.04 18.1.0
  • Clarified default location of .sdc and .qsf files in "Constraining Designs" topic.
  • Added two new "Assigning a Pin" and "Creating a Project and Applying Constraints" topics showing Tcl examples.
2018.09.24 18.1.0 Initial release in Intel Quartus Prime Standard Edition User Guide.
2017.11.06 17.1.0
  • Renamed topic: Constraining Designs with the GUI to Constraining Designs with Quartus Prime Tools.
  • Renamed topic: Global Constraints to Global Constraints and Assignments.
  • Added table: Quartus Prime Tools to Set Global Constraints.
  • Removed topic: Common Types of Global Constraints.
  • Removed topic: Settings That Direct Compilation and Analysis Flows.
  • Updated topic: Node, Entity and Instance-Level Constraints.
  • Added table: Quartus Prime Tools to Set Node, Entity and Instance Level Constraints.
  • Added topic: Assignment Editor.
  • Updated topic: Constraining Designs with the Pin Planner.
  • Updated topic: Constraining Designs with the Chip Planner.
  • Added topic: Constraining designs with the Design Partition Planner.
  • Updated topic: Probing Between Components of the Quartus Prime GUI.
  • Added example: Locate a Resource Selected in the Project Navigator.
  • Updated topic: SDC and the Timing Analyzer, and renamed to Specifying Individual Timing Constraints.
  • Added figure: Constraint Menu in Timing Analyzer.
  • Added example: Create Clock Dialog Box.
  • Updated topic: Constraining Designs with Tcl, and renamed to Constraining Designs with Tcl Scripts
  • Updated topic: Quartus Prime Settings Files and Tcl , and renamed to Generating Quartus Prime Settings Files.
  • Added example: blinking_led.qsf File.
  • Updated topic: Timing Analysis with Synopsys Design Constraints and Tcl, and renamed to Timing Analysis with .sdc Files and Tcl Scripts.
  • Added example: .sdc File with Timing Constraints.
  • Added topic: Tcl-only Script Flows.
  • Updated topic: A Fully Iterative Scripted Flow.
2015.11.02 15.1.0
  • Changed instances of Quartus II to Intel Quartus Prime.
June 2014 14.0.0 Formatting updates.
November 2012 12.1.0 Update Pin Planner description for task and report windows.
June 2012 12.0.0 Removed survey link.
November 2011 10.0.2 Template update.
December 2010 10.0.1 Template update.
July 2010 10.0.0 Rewrote chapter to more broadly cover all design constraint methods. Removed procedural steps and user interface details, and replaced with links to Quartus II Help.
November 2009 9.1.0
  • Added two notes.
  • Minor text edits.
March 2009 9.0.0
  • Revised and reorganized the entire chapter.
  • Added section “Probing to Source Design Files and Other Quartus Windows” on page1–2.
  • Added description of node type icons (Table1–3).
  • Added explanation of wildcard characters.
November 2008 8.1.0 Changed to 8½” × 11” page size. No change to content.
May 2008 8.0.0 Updated Quartus II software 8.0 revision and date.
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