Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

ID 683492
Date 1/10/2019
Public
Document Table of Contents

2.4.2. Checking I/O Pin Assignments in Real-Time

Live I/O check validates I/O assignments against basic I/O buffer rules in real time. The Pin Planner immediately reports warnings or errors about assignments as you enter them. The Live I/O Check Status window displays the total number of errors and warnings. Use this analysis to quickly correct basic errors before proceeding. Run full I/O assignment analysis when you are ready to validate pin assignments against the complete set of I/O system rules.
Note: Live I/O check is supported only for Arria® II, Cyclone® IV, MAX® II, and Stratix® IV device families.

Live I/O check validates against the following basic I/O buffer rules:

  • VCCIO and VREF voltage compatibility rules
  • Electromigration (current density) rules
  • Simultaneous Switching Output (SSO) rules
  • I/O property compatibility rules, such as drive strength compatibility, I/O standard compatibility, PCI_IO clamp diode compatibility, and I/O direction compatibility
  • Illegal location assignments:
    • An I/O bank or VREF group with no available pins
    • The negative pin of a differential pair if the positive pin of the differential pair is assigned with a node name with a differential I/O standard
    • Pin locations that do not support the I/O standard assigned to the selected node name
    • For HSTL- and SSTL-type I/O standards, VREF groups of a different VREF voltage than the selected node name.

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