Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

ID 683492
Date 1/10/2019
Public
Document Table of Contents

1.1.2. Node, Entity, and Instance-Level Constraints

Node, entity, and instance-level constraints apply to a subset of the design hierarchy. These constraints take precedence over any global assignment that affects the same sections of the design hierarchy. The following tools are available in the Intel® Quartus® Prime software to specify node, entity, and instance-level constraints:

Although you can specify constraints using a variety of tools, the following table shows the most effective constraint tools at each design phase:

Table 2.  Constraint Tools per Design Phase
Design Phase Assignment Editor Interface Planner Tile Interface Planner Chip Planner Timing Analyzer Pin Planner
Pre-Synthesis X   X     X
Post-Synthesis X X   X    
Post-Fit X     X X  
Table 3.   Intel® Quartus® Prime Standard Edition Tools to Set Node, Entity and Instance Level Constraints
Assignment Type Example Assignment Editor Chip Planner Pin Planner
Pin Project files X   X
Location
  • Device Family
  • Top-level Entity
X X  
Routing
  • Device
  • Fitter Effort
  • IO Standard
X X  
Simulation Vector input source X X X

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