2.1. I/O Planning Overview 2.2. Assigning I/O Pins 2.3. Importing and Exporting I/O Pin Assignments 2.4. Validating Pin Assignments 2.5. Verifying I/O Timing 2.6. Viewing Routing and Timing Delays 2.7. Analyzing Simultaneous Switching Noise 2.8. Scripting API 2.9. Managing Device I/O Pins Revision History
2.1.1. Basic I/O Planning Flow
The following steps describe the basic flow for assigning and verifying I/O pin assignments:
- Click Assignments > Device and select a target device that meets your logic, performance, and I/O requirements. Consider and specify I/O standards, voltage and power supply requirements, and available I/O pins.
- Click Assignments > Pin Planner.
- To setup a top-level HDL wrapper file that defines early port and interface information for your design, click Early Pin Planning in the Tasks pane.
- Click Import IP Core to import any defined IP core, and then assign signals to the interface IP nodes.
- Click Set Up Top-Level File and assign user nodes to device pins. User nodes become virtual pins in the top-level file and are not assigned to device pins.
- Click Generate Top-Level File. Use top-level file to validate I/O assignments.
- Assign I/O properties to match your device and PCB characteristics, including assigning logic, I/O standards, output loading, slew rate, and current strength.
- Click Run I/O Assignment Analysis in the Tasks pane to validate assignments and generate a synthesized design netlist. Correct any problems reported.
- Click Processing > Start Compilation. During compilation, the Intel® Quartus® Prime software runs I/O assignment analysis.
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