Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

ID 683492
Date 1/10/2019
Document Table of Contents

2.1.1. Basic I/O Planning Flow

The following steps describe the basic flow for assigning and verifying I/O pin assignments:
  1. Click Assignments > Device and select a target device that meets your logic, performance, and I/O requirements. Consider and specify I/O standards, voltage and power supply requirements, and available I/O pins.
  2. Click Assignments > Pin Planner.
  3. To setup a top-level HDL wrapper file that defines early port and interface information for your design, click Early Pin Planning in the Tasks pane.
    1. Click Import IP Core to import any defined IP core, and then assign signals to the interface IP nodes.
    2. Click Set Up Top-Level File and assign user nodes to device pins. User nodes become virtual pins in the top-level file and are not assigned to device pins.
    3. Click Generate Top-Level File. Use top-level file to validate I/O assignments.
  4. Assign I/O properties to match your device and PCB characteristics, including assigning logic, I/O standards, output loading, slew rate, and current strength.
  5. Click Run I/O Assignment Analysis in the Tasks pane to validate assignments and generate a synthesized design netlist. Correct any problems reported.
  6. Click Processing > Start Compilation. During compilation, the Intel® Quartus® Prime software runs I/O assignment analysis.