Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

ID 683492
Date 1/10/2019
Public
Document Table of Contents

2.5.1.5. Advanced I/O Timing Analysis Reports

The following reports show advanced I/O timing analysis information:

Table 12.  Advanced I/O Timing Reports
I/O Timing Report Description
Timing Analyzer Report Reports signal integrity and board delay data.
Board Trace Model Assignments report Summarizes the board trace model component settings for each output and bidirectional signal.
Signal Integrity Metrics report Contains all the signal integrity metrics calculated during advanced I/O timing analysis based on the board trace model settings for each output or bidirectional pin. Includes measurements at both the FPGA pin and at the far-end load of board delay, steady state voltages, and rise and fall times.
Note: By default, the Timing Analyzer generates the Slow‑Corner Signal Integrity Metrics report. To generate a Fast-Corner Signal Integrity Metrics report you must change the delay model by clicking Tools > Timing Analyzer.

Did you find the information on this page useful?

Characters remaining:

Feedback Message