Power Distribution Network

The easy-to-use power distribution network (PDN) design tool is a graphical tool used with all Intel® FPGAs to optimize the board-level PDN. The purpose of the board-level PDN is to distribute power and return currents from the voltage regulating module (VRM) to the FPGA power supplies, and support optimal transceiver signal integrity and FPGA performance.

Power Distribution Network Model

For each power supply, you must choose a network of bulk and ceramic decoupling capacitors. While you can use SPICE simulation to simulate the circuit, the PDN design tool provides a fast, accurate, and interactive way to determine the right number of decoupling capacitors for optimal cost and performance trade-offs. By determining the optimal set of decoupling capacitors for a given design, you can save board space and ease the board layout process.

You can select the number and values of the capacitors in the spreadsheet (see Figure 1), and the tool calculates the composite impedance of the PDN along with the impedance characteristics of the VRM, the decoupling capacitors and their mounting inductance, the PCB, and the FPGA with on-package and on-chip capacitors.

To achieve optimal performance, the composite impedance must meet the target impedance (see Figure 2) up until the PCB cutoff frequency (FEFFECTIVE). The target impedance is derived from FPGA power requirements. The Power Analyzer in the Intel Quartus® Prime and Quartus II development software allows you to accurately analyze the FPGA's power consumption for each power rail.

The PDN printed circuit board design methodology is described in detail in AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology (PDF). It also describes the role of the FEFFECTIVE in designing an efficient system power delivery solution.

Design with confidence using our tools and board design guidelines and get your design right the first time with the right performance and cost trade-offs.

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