Intel® FPGA Design Examples

Search Altera content collection of development guides, training, software downloads and software kits for FPGA.

MAX II and MAX CPLD Design Examples demonstrate various features of the MAX II and MAX low-power CPLD families using Quartus II or MAX+PLUS II software.

Discover download files, system requirements, and support information for the FPGA Design Security Solution Using a Secure Memory Device reference design.

The Intel drive-on-a-chip motor control reference design is an integrated drive system on a single Cyclone V SoC or Intel MAX 10. Learn more in this guide.

OpenCL Mandelbrot Fractal Algorithm example provides a kernel that implements the Mandelbrot fractal algorithm as well as a host application that displays the results to the screen.

Single-Port Triple-Speed Ethernet On-Board PHY Chip datapath reference design provides a simple and quick way to implement your own Ethernet-based design in an Intel FPGA.

10-Gbps Ethernet Hardware Demonstration reference design provides a quick way to implement your 10-Gbps Ethernet (10GbE)-based design in an Intel FPGA.

This example describes a 64 bit x 8 bit synchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in VHDL.

This example describes a 64-bit x 8-bit single clock synchronous RAM design with different read and write addresses in VHDL. Learn more about this design from Intel.

Intel provides a variety of ready-to-use design samples like the Interface Serial Design Examples to deliver efficient solutions for your application.

Intel provides a variety of ready-to-use design samples like the Ethernet Design Examples to deliver efficient solutions for your application.

A VHDL State Machine is a sequential circuit that advances through a number of states. The examples provide the VHDL codes to implement the following types of state machines.