Intel® FPGA Design Examples

This example describes a two-input, 8 bit adder/subtractor design in VHDL. The design unit dynamically switches between add and subtract operations.

This example describes a 64 bit x 8 bit synchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in VHDL.

A VHDL State Machine is a sequential circuit that advances through a number of states. The examples provide the VHDL codes to implement the following types of state machines.

This example describes a 64-bit x 8-bit single-port RAM design with common read and write addresses in VHDL. Learn more about this design from Intel.

This example describes a 64-bit x 8-bit single clock synchronous RAM design with different read and write addresses in VHDL. Learn more about this design from Intel.

This template shows how to infer digital signal processing (DSP) blocks with different features from VHDL code. Recommended for Stratix III and Stratix IV FPGA devices.

This example describes a 64-bit x 8-bit dual clock synchronous RAM design with different read and write addresses in VHDL. Learn more about the synchronous design from Intel.

This example describes a 16-bit binary adder tree in VHDL. Devices with 4-input lookup tables in logic elements (LEs) can improve performance with a binary adder tree structure.

The VHDL 8x64 Shift Register with Taps example describes an 8-bit wide, 64-bit long shift register with equally spaced taps in VHDL. Learn more from Intel.

This VHDL 1x64 shift register design example describes a single-bit wide, 64-bit long shift register in VHDL. Learn more about this design from Intel.

Search Intel's content collection of development guides, training, software downloads and software kits for FPGA SDK for OpenCL.

Discover download files, system requirements, and support information for the FPGA Design Security Solution Using a Secure Memory Device reference design.