Intel® FPGA Design Examples

Digital blocks offers a TFT LCD controller reference design.

Triple-rate SDI reference design.

OpenCL™ channelizer design example.

Nios® II design example web page for Cyclone® III 3C25 LCD controller system.

Avalon® memory-mapped primary templates.

Digital data rate down conversion system design example using CIC and FIR filters.

DSP builder for Intel® FPGAs.

Timing analyzer UI description.

PCI* Express to external memory reference design.

PCI* Express, PCIe*, Gen2, high-performance, DMA, Avalon®-MM.

10-Gbps ethernet hardware demonstration reference design.

The shared memory partion design example configures the memory protection rules in the hard processor system (HPS) SDRAM controller.