Intel® FPGA Design Examples

Run-time reconfigurable scaler design example.

This example design demonstrates how to accelerate your Nios® II processor networking applications.

This example demonstrates how to use the Nios® II C2H compiler to accelerate an image rotation algorithm in C.

Digital Up-Conversion with IF Carrier Frequency

This example shows the use of the Avalon® Streaming (Avalon-ST) pass-through interface in RapidIO® as a platform.

This example describes an 8-bit unsigned multiply-adder design with registered I/O ports in VHDL.

This example describes an 8-bit signed multiply-accumulator design with I/O ports and a synchronous load input in VHDL.

This examples describes a 8-bit counter with an synchronous reset input in VHDL.

This example describes a parameterized ternary adder tree in Verilog HDL.

This example describes a 16-bit binary adder tree in Verilog HDL.

The design allows microcontroller I/O expansion in microcontroller or microprocessor-based systems with MAX® 3000A.

Multicycle example.