Intel® FPGA Design Examples
Intel® design examples provide efficient solutions for common design challenges. These designs can be used as a starting point for developing with your unique system and are available using many functions such as filters, arithmetic functions, error detection/correction, modulation/demodulation, and video and image processing.
Design examples are also available in the Design Store for Intel® FPGAs and RocketBoards.org.
PCI Express* (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 16.0 GT/s.
FPGA Design Store | Intel
Download design examples and reference designs for Intel® FPGAs and development kits.
The Intel drive-on-a-chip motor control reference design is an integrated drive system on a single Cyclone V SoC or Intel MAX 10. Learn more in this guide.
This design example shows you how to use the Cyclone® III RSU feature in AP mode.
Intel offers a PCI Express (PCIe*) to External Memory reference design that demonstrates the operation of PCIe-based MegaCore function with a DDR2 or DDR3 SDRAM memory controller.
Single-Port Triple-Speed Ethernet On-Board PHY Chip datapath reference design provides a simple and quick way to implement your own Ethernet-based design in an Intel FPGA.
10-Gbps Ethernet Hardware Demonstration reference design provides a quick way to implement your 10-Gbps Ethernet (10GbE)-based design in an Intel FPGA.
This example describes a two-input, 8 bit adder/subtractor design in VHDL. The design unit dynamically switches between add and subtract operations.
This example describes a 64 bit x 8 bit synchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in VHDL.
A VHDL State Machine is a sequential circuit that advances through a number of states. The examples provide the VHDL codes to implement the following types of state machines.
This example describes a 64-bit x 8-bit single-port RAM design with common read and write addresses in VHDL. Learn more about this design from Intel.
This example describes a 64-bit x 8-bit single clock synchronous RAM design with different read and write addresses in VHDL. Learn more about this design from Intel.