Intel® FPGA Design Examples

This design example shows you how to use the Cyclone® III RSU feature in AP mode.

Intel offers a PCI Express (PCIe*) to External Memory reference design that demonstrates the operation of PCIe-based MegaCore function with a DDR2 or DDR3 SDRAM memory controller.

Single-Port Triple-Speed Ethernet On-Board PHY Chip datapath reference design provides a simple and quick way to implement your own Ethernet-based design in an Intel FPGA.

10-Gbps Ethernet Hardware Demonstration reference design provides a quick way to implement your 10-Gbps Ethernet (10GbE)-based design in an Intel FPGA.

This example describes a two-input, 8 bit adder/subtractor design in VHDL. The design unit dynamically switches between add and subtract operations.

This example describes a 64 bit x 8 bit synchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in VHDL.

A VHDL State Machine is a sequential circuit that advances through a number of states. The examples provide the VHDL codes to implement the following types of state machines.

This example describes a 64-bit x 8-bit single-port RAM design with common read and write addresses in VHDL. Learn more about this design from Intel.

This example describes a 64-bit x 8-bit single clock synchronous RAM design with different read and write addresses in VHDL. Learn more about this design from Intel.

This template shows how to infer digital signal processing (DSP) blocks with different features from VHDL code. Recommended for Stratix III and Stratix IV FPGA devices.

This example describes a 64-bit x 8-bit dual clock synchronous RAM design with different read and write addresses in VHDL. Learn more about the synchronous design from Intel.

This example describes a 16-bit binary adder tree in VHDL. Devices with 4-input lookup tables in logic elements (LEs) can improve performance with a binary adder tree structure.