VHDL: Adder/Subtractor

BUILT IN - ARTICLE INTRO SECOND COMPONENT

This example describes a two input parameterized adder/subtractor design in VHDL. The design unit multiplexes add and subtract operations with an addnsub input. Synthesis tools detect add and subtract units in HDL code that share inputs and whose outputs are multiplexed by a common signal. Software infers lpm_addsub megafunction for such add/subtract designs.

Figure 1. Adder/subtractor top-level diagram.

Download the files used in this example:

Table 1. Adder/Subtractor Port Listing

Port Name

Type

Description

a[4:0], b[4:0]

Input

4-bit data inputs to adder/subtractor

addnsub

Input

Multiplexing input for add and subtract operations

result[5..0]

Output

5-bit output along with 1 bit carry/borrow