This example describes an 8-bit wide, 64-bit long shift register with equally spaced taps in VHDL. Synthesis tools detect groups of shift registers and infer altshift_taps megafunction depending on the target device architecture.
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Table 1. 8x64 Shift Register Port Listing
| Port Name | Type | Description |
|---|---|---|
| clk | Input | Clock |
| shift | Input | Shift enable input |
| sr_in[7..0] | Input | 8-bit shift register input |
| sr_tap_one[7:0] | Output | 8-bit output of first tap |
| sr_tap_two[7:0] | Output | 8-bit output of second tap |
| sr_tap_three[7:0] | Output | 8-bit output of third tap |
| sr_out[7:0] | Output | 8-bit shift register output |