The Intel drive-on-a-chip motor control reference design is an integrated drive system on a single Cyclone® V SoC or Intel® MAX® 10. The design implements single- and multiaxis field-oriented control (FOC) supporting concurrent control of up to four permanent magnet synchronous motors. The reference design showcases a software-centric design flow for motor control on FPGAs. It targets either the dual arm* Cortex*-A9 hard processor system or the Nios® II soft-core processor as the drive system host integrated with DSP co-processors and key motor control interface IP in the FPGA. This demonstrates the cost-effective scalability of integrated drive-on-a-chip designs on Intel's Cyclone® families and is an excellent starting point for your own drive system design.
- Complete software system running on either the dual arm Cortex-A9 hard processor system or Nios II processor, performing high-level control and configuration (in addition to closing of motor position and speed loops).
- Software-only and FPGA-accelerated FOC implementations that integrate position and speed loops in software with an ultra-low latency, high-performance current control loop in the FPGA as a DSP coprocessor.
- Optimized and software-configurable FOC IP subsystem, customizable in DSP Builder with support for both fixed- and floating-point precision implementations.
- Integrates key motor control functions such as space vector pulse-width modulation (PWM), Sigma-Delta ADC interface and filter logic, and position feedback encoder interfaces in the FPGA, all under control of software.
- Intel Multiaxis Motor Control Board with either Cyclone V Development Kit or INK Development Kit from Terasic
The reference design, as shown in Figure 1, implements a software-configurable field-oriented-control (FOC) algorithm for concurrent control of up to two permanent magnet synchronous motors integrated with key motor control interface intellectual property (IP).