DSP Builder for Intel® FPGAs

Overview

DSP Builder for Intel® FPGAs is a digital signal processing (DSP) design tool that enables Hardware Description Language (HDL) generation of DSP algorithms directly from the MathWorks Simulink* environment onto Intel® FPGAs. The tool generates high quality, synthesizable VHDL/Verilog code from MATLAB functions and Simulink models. The generated Register Transfer Level (RTL) code can be used for Intel® FPGA programming. DSP Builder for Intel® FPGAs is widely used in radar designs, wireless and wireline communication designs, medical imaging, and motor control applications.

Pricing and Licensing Information

Learn more about fixed/floating subscription options for the DSP development tool.

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Get an Evaluation License

Obtain your 30-day trial software from MathWorks for use with DSP Builder for Intel® FPGAs.

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Download Software

Download DSP Builder for Intel® FPGAs.

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Features

DSP Builder for Intel® FPGAs enables the implementation of DSP designs with high performance and productivity benefits. Here are some highlighted features:

  • Import RTL into your MathWorks* MATLAB/Simulink environment for co-simulation and code generation
  • Go from high-level schematic to low-level optimized VHDL targeted for Intel® FPGAs
  • Perform high-performance fixed- and floating-point digital signal processing (DSP) with vector processing, such as complex IEEE 754 single-precision floating point
  • Perform push-button design migration to Intel's hard floating-point DSP block in Intel® Arria® 10 and Intel® Stratix® 10 devices
  • Build custom arithmetic logic unit (ALU) processor architectures from a flat data-rate design with ALU folding
  • Perform high-level synthesis optimizations, auto-pipeline insertion and balancing, and targeted hardware mapping
  • Build custom fast Fourier transform (FFT) algorithms using a flexible ‘white-box’ fast Fourier transform (FFT) toolkit with an open hierarchy of libraries and blocks
  • Use a designer-specified system clock constraint to automatically pipeline, time-division multiplex/fold, and close timing
  • Access advanced math.h functions and multichannel data
  • Generate resource utilization tables for all designs without a Intel® Quartus® Prime Software compile
  • Automatically generate projects or scripts for the Intel® Quartus® Prime Software, Timing Analyzer, Platform Designer (formerly Qsys), and ModelSim*-Intel® FPGA Edition

What's New in 19.1

  • Added support for For-Loop blocks in C model export capability
  • Improved pipelining into very wide width-stitched memories resulting in higher quality of results
  • Improved integration of DSP Builder IP in Platform Designer

Getting Started

  •  Supported with the Intel® Quartus® Prime Design Software Pro/Standard Edition software. 
  • Download Pro Edition to target the latest Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices
  • Download Standard Edition to target Intel® Arria® 10, Stratix® V, Cyclone® V, Intel® Cyclone® 10 LP, and Intel® MAX® 10 devices
  • Additional DSP Builder and MATLAB licenses are required. Purchase DSP Builder license here. Purchase MATLAB license here
  • Required order of installation is
         1. Intel® Quartus® Prime
         2. MathWorks*
         3. DSP Builder for Intel® FPGAs
  • DSP Builder version history and software requirements
  • Learn how to add your DSP Builder license to your MATLAB installation

Documentation and Support


Find technical documentation, videos, and training courses for DSP Builder for Intel® FPGAs.