DSP Builder for Intel® FPGAs
Overview
Features
Provides Ease of Use
- Perform push-button design migration to the hardened fixed- and floating-point DSP block in Arria® 10, Stratix® 10, and Agilex™ device families.
- Automatically generate projects and verification scripts for the Quartus® Prime Design Software, Timing Analyzer, Platform Designer, and Questa*-Intel® FPGA Edition.
- Generate resource utilization tables for your designs without requiring a Quartus® Prime compile.
Reduces Time to Design Success
- Perform high-level synthesis optimizations, auto-pipeline insertion and balancing, and targeted hardware mapping.
- Use a designer-specified system clock constraint to control the automatic pipelining and time-division multiplex/folding.
- Access highly configurable FFTs, FIRs, and advanced mathematical functions.
- Import RTL into your MathWorks MATLAB/Simulink environment for co-simulation and code generation.
- Build custom arithmetic logic unit (ALU) processor architectures from a flat data-rate design with ALU folding.
Get Started
Required order of installation:
- MathWorks MATLAB and Simulink.
- Quartus® Prime Design Software.
- DSP Builder for Intel® FPGAs.
Step 1
DSP Builder for Intel FPGAs requires MathWorks software. Learn how to add your DSP Builder license to your MATLAB installation.
Contact MathWorks to obtain a 30-day trial software license.
Tool Integration
Simulink (Mathworks)
DSP Builder is interoperable with other Simulink blocksets. You can use the basic Simulink blockset to create interactive testbenches which allow you to compare the behavior of your DSP Builder design with a reference result that you provide.
Quartus® Prime Design Software
DSP Builder allows you to build high-speed, high-performance DSP datapaths with automatic pipeline register insertion. You then use the Quartus Prime design software to complete the synthesis and place-and-route process for your target FPGA device.
Platform Designer
DSP Builder creates a conduit interface and component description file (hw.tcl) for each design. DSP Builder creates a memory-mapped interface only if the design contains interface blocks or external memory blocks. DSP Builder can also create an Avalon® Streaming interface. The hw.tcl file can expose the processor bus for connection in Platform Designer.
Questa*-Intel® FPGA Edition Software
If the Questa executable is in your path, you can run the Questa simulator from within DSP Builder. The automatic testbench flow generates and runs a test script which allows you to compare Simulink simulation results with the output of the RTL simulator that simulates the generated HDL.
Support
Documentation Support
Read DSP documentation to get more information.
Licensing Support
Get licensing support information at Intel® FPGA Licensing Support Center.
DSP IP Cores
Browse available DSP IPs.
Additional Resources
Download
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Licensing
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Training
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