DSP Builder for Intel® FPGAs enables the implementation of DSP designs with high performance and productivity benefits. Here are some highlighted features:
- Import RTL into your MathWorks MATLAB/Simulink environment for co-simulation and code generation.
- Go from high-level schematic to low-level optimized VHDL targeted for Intel® FPGAs.
- Perform high-performance fixed- and floating-point digital signal processing (DSP) with vector processing, such as complex IEEE 754 single-precision floating point.
- Perform push-button design migration to Intel's hard floating-point DSP block in Intel® Arria® 10 and Intel® Stratix® 10 devices.
- Build custom arithmetic logic unit (ALU) processor architectures from a flat data-rate design with ALU folding.
- Perform high-level synthesis optimizations, auto-pipeline insertion and balancing, and targeted hardware mapping.
- Build custom fast Fourier transform (FFT) algorithms using a flexible ‘white-box’ fast Fourier transform (FFT) toolkit with an open hierarchy of libraries and blocks.
- Use a designer-specified system clock constraint to automatically pipeline, time-division multiplex/fold, and close timing.
- Access advanced math.h functions and multichannel data.
- Generate resource utilization tables for all designs without a Intel® Quartus® Prime Software compile.
- Automatically generate projects or scripts for the Intel® Quartus® Prime Software, Timing Analyzer, Platform Designer (formerly Qsys), and ModelSim*-Intel® FPGA Edition.