Platform Designer (formerly Qsys)

The Platform Designer (formerly Qsys) is the next-generation system integration tool in the Intel^® Quartus^® Prime software. The Platform Designer saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. The Platform Designer utilizes a powerful hierarchical framework to offer fast response times for interconnecting large systems, while also providing support for blackbox entities. This enables Platform Designer to provide fast response times while opening systems and creating new connections by regenerating or operating on IP blocks that have changed^†. The new Platform Designer tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, to schematic entry, and black boxes.

Platform Designer in the Pro Edition of the Intel Quartus Prime software, expands the ease of use, flexibility, and performance of the standard Platform Designer system design tool. Our training course, System Design with Platform Designer Pro, explores the differences between the Intel Quartus Prime Standard and Pro Edition software versions of the tools, focusing on Platform Designer support for generic components in the Pro Edition - the idea that every component in a system design is essentially a blackbox defined by its interface and signal connections to the rest of the system. Separating components from the system design in this way helps with team-based design and version control. You'll learn about the new features of the tool that support generic components and how to validate the integrity of a system.

In the Intel Quartus Prime Pro Edition software v18.0, the Platform Designer supports the new features that greatly help with design portability. You can now:

Allow coherency signals from Stratix 10 HPS interface to be transported to IP via ACE-Lite support
Generate hierarchical simulation scripts by referencing simulation information of its subsystems and IP components without traversing system hierarchy
Use Verilog syntax to connect ports in Platform Designer with wire-level connectivity
Incorporate IP components that use SystemVerilog interfaces into Platform Designer systems
Experience significant reduction in IP upgrade regeneration time
More details on all these features are available in the Platform Designer User Guide

Also, please watch the Platform Designer overview video that walks through the process of using the tool...

Platform Designer (Standard / Platform Designer Pro)	Platform Designer (Standard) / Platform Designer Pro Advantages
Faster development	Easy-to-use GUI interface enables quick integration between IP functions and subsystems Automatic generation of interconnect logic (address/data bus connections, bus width matching logic, address decoder logic, arbitration logic, etc.) Availability of plug-and-play Platform Designer-compliant IP. (Note: Platform Designer-Pro compliance is not available for all IP) Support mixing of different industry-standard interfaces including Avalon^®, ARM* AMBA* AXI, AMBA APB, and AMBA AHB* interfaces Automatic HDL generation of your system Hierarchical design flow enables scalable designs, team-based design, and maximizes design reuse Migration flow to Platform Designer (does not apply to Platform Designer Pro) for SOPC Builder designs (view demo)
Faster timing closure	High-performance Platform Designer (Standard) interconnect based on the NoC architecture and automatic pipelining delivers higher performance compared to SOPC Builder’s system interconnect fabric (view demo)^† Ability to control the aggressiveness of automatic pipelining to meet f_MAX and latency system requirements
Faster verification	Ability to start your simulation faster with automatic testbench generation and by using the verification IP suite Faster board bring-up with System Console by sending read and write transactions into a live system (view demo)

Platform Designer Resources:

Platform Designer documentation and tool support
White paper: Applying the Benefits of Network on a Chip Architecture to FPGA System Design (PDF)
Platform Designer-compliant IP
System Console for real-time debug of your Platform Designer (formerly Qsys) system

Getting Started:

Complete Platform Designer (Standard) tutorial design example
Register for a Platform Designer (formerly Qsys) (Standard) training class
View Platform Designer (formerly Qsys) (Standard) reference designs
Download Intel Quartus Prime software (includes Platform Designer - Standard)

Demonstrations

	AMBA AXI and Altera Avalon Interoperation Using Platform Designer (Standard) See how seamless it is to integrate IP components with AMBA AXI interfaces with Avalon interfaces using the Platform Designer (Standard). View demo
	Increase Interconnect Performance with Platform Designer (Standard) See how you can improve the performance of the Platform Designer (Standard) interconnect with automatic register pipelining. View demo
	Board Bring-Up with System Console See how you can bring up your board with a few simple checks Learn how to quickly isolate issues by checking your system’s resets and clocks, and by performing simple address-based read and write transactions View demo
	Building a Custom GUI with System Console See how you can build your own custom GUI to debug and monitor your system Learn how to add different graphical elements to control and monitor your system View demo

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.