AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents
Give Feedback

1. About the Drive-On-Chip Design Example for Cyclone V Devices

The design demonstrates concurrent multiaxis control of two three-phase permanent magnet synchronous motors (PMSMs) or sinusoidally wound brushless DC (BLDC) motors.

The design targets a Cyclone V SoC development board. The board can take power from a standard power supply or from a rechargeable battery pack, which shows the bidirectional power flow and battery state-of-charge estimation features.

AC and servo drive system designs comprise multiple distinct but interdependent functions to realize requirements to meet the performance and efficiency demands of modern motor control systems. The system's primary function is to efficiently control the torque and speed of the AC motor through appropriate control of power electronics. A typical drive system includes the following items:

  • Flexible pulse-width modulation (PWM) circuitry to switch the power stage transistors appropriately
  • Motor control loops for single- or multiaxis control
  • Industrial networking interfaces
  • Position encoder interfaces
  • Current, voltage, and temperature measurement feedback elements.
  • Monitoring functions, for example, for vibration suppression.

The system requires system software running on a processor for high-level system control, coordination, and management.

Cyclone® devices offer high-performance fixed- and floating-point DSP functionality. Cyclone V SoC devices offer the integrated ARM-based hard processor subsystem (HPS). Cyclone FPGA devices offer a scalable and flexible platform for integration of single- and multiaxis drives on a single FPGA. The Intel motor control development framework allows you to create these integrated systems easily. The framework provides a design that comprises IPs, software libraries, and a hardware platform. The framework seamlessly integrates Intel system-level design tools such as DSP Builder and Qsys, and software and IP components that allow you to extend and customize the design to meet your own application needs. The framework also supports optimal partitioning decisions between software running on an integrated processor and IP performing portions of the motor control algorithm in the FPGA, to accelerate performance as required. For example, depending on the performance requirements of your system or the number of axes you need to support, you may implement all the inner current control loop in hardware or entirely in software. The framework flexibly allows you to connect to the motor and power stages through off-chip ADCs, and feedback encoder devices and to connect to higher-level automation controllers through off-the-shelf digital encoder and industrial Ethernet IP cores, respectively.

The design offers vibration suppression. The design demonstrates how you can implement standard components (FFTs, FFT-post processing, IIR filter), to enable you to develop an automatic method for vibration suppression. You may use the FFTs and FFT postprocessing for condition monitoring, which detects vibrations that indicate degradation or wear and communicate the results to another system.

The design integrates Motor Control IP Suite components, an ARM-based HPS, and software that uses an FOC algorithm. The design uses the Intel DSP Builder system-level design tool to implement the FOC algorithm.

DSP Builder provides a MATLAB and Simulink flow that allows you to create hardware optimized fixed latency representations of algorithms without requiring HDL/hardware skills. Intel provides DSP Builder fixed-point and floating point algorithms to demonstrate both options. The DSP Builder folding feature reduces the resource usage of the logic as an alternative to a fully parallel implementation. The design also includes an efficient Avalon® Memory-Mapped interface that you can integrate in Qsys.