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1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices
4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices
4.3. Setting Up the Motor Control Board with your Development Board
4.4. Programming the Hardware onto the Device
4.5. Setting Up Terminal Emulator
4.6. Downloading the HPS Software to the Device
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example
6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example
6.3. Vibration Suppression Tab
6.4. Controlling the DC-DC Converter
6.5. Tuning the PI Controller Gains
6.6. Controlling the Speed and Position Demonstrations
6.7. Monitoring Performance
9.1. Processor Subsystem
9.2. Six-channel PWM Interface
9.3. DC Link Monitor
9.4. Drive System Monitor
9.5. Quadrature Encoder Interface
9.6. Sigma-Delta ADC Interface for Drive Axes
9.7. DC-DC Converter
9.8. Motor Control Modes
9.9. FOC Subsystem
9.10. FFTs
9.11. DEKF Technique for Battery Management
9.12. Signals
9.13. Registers
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
9.9.2. Avalon Memory-Mapped Interface
9.9.3. About DSP Builder for Intel FPGAs
9.9.4. DSP Builder for Intel FPGAs Folding
9.9.5. DSP Builder for Intel FPGAs Model Resource Usage
9.9.6. DSP Builder for Intel FPGAs Design Guidelines
9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
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6.3.3. FFT0 and FFT1 Graphs
On the Vibration Suppression tab, System Console displays the following graphs:
- Input signal to FFT0 against time.
- The magnitude of FFT0 against frequency.
- Input signal to FFT1 against time.
- The magnitude of FFT1 against frequency.
The graphs update at the same time as the graphs on the Control and Diagnostics tab whenever the trigger function in that tab activates. Within the SoC, the 4,096pt FFT data recalculates after every 64 new data points. The data sample rate is 16 kHz, thus the FFTs recalculate at 250 Hz.
System Console saves both the time- and frequency-based data to the .csv file that you specify in the Control and Diagnostics tab. You can then verify offline the correctness of the FFT calculation.
The FFT magnitude data is in dB (i.e. 20*log10 absolute value in physical units) similar to a control system Bode plot.
A basic peak detection algorithm enables you to measure particular peaks and develop automated vibration suppression. For each of the two FFTs, the algorithm finds the maximum magnitude value between two specified frequency limits. Thus, you can search for peaks within a physically relevant range without seeing large FFT magnitudes that often occur at low frequencies. System Console shows the peaks with a cross-hair superimposed on the FFT magnitude graph. It shows the frequency and magnitude values below the graph.
Figure 19. Using the Graphs
You can zoom into an area of the graph by clicking and dragging the cursor over that area. To return to the original scaling, right-click on the graph and select Auto Range, Both Axes.'