AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

9.7.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format

Signals for the Drive-on-Chip Design Example.
Table 16.  DC-DC Model and VHDL Entity Signal Names and Data Format
Signal Name Data Format Scaling Default/Notes
Inputs
In1 ufix1 0
In2 ufix8 0
CMD_DC_In ufix14 1 V = 1 48
voltage_fdbk sfix13 0.025 V = 1 or 1 V = 40
current_fdbk_a sfix13 0.01 A = 1 or 1 A = 100
current_fdbk_b sfix13 0.01 A = 1 or 1 A = 100
freq_khz ufix14 62
enable ufix1 1
open_0_close_1 ufix1 1
duty_0_100 ufix14
pwm_sync_n ufix1 1 (low to reset PWM counter)
pgain_voltage ufix14 1/100 300 (* 1/100 = 3)
igain_voltage ufix14 1e-7 (1/fclk) 4000
pgain_current ufix14 1/1000 20 (* 1/1000 = 0/02)
igain_current ufix14 1e-7 (1/fclk) 25
clk std_logic 20 MHz
bidir_en ufix1 0 for PS, 1 for battery
areset std_logic 0
Outputs
out1 ufix1
out2 ufix8
gate_a_h ufix1 MOSFET gate signal
gate_a_l ufix1 MOSFET gate signal
gate_b_h ufix1 MOSFET gate signal
gate_b_l ufix1 MOSFET gate signal
ov ufix1 High = overvoltage
oc ufix1 High = overcurrent

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