9.9.5. DSP Builder for Intel FPGAs Model Resource Usage
Intel compared floating- and fixed-point versions of the FOC algorithm with and without folding. In addition, Intel compared using a 26-bit (17-bit mantissa) instead of standard single-precision 32-bit (23-bit mantissa) floating point implementation. 26-bit is a standard type within DSP Builder for Intel FPGAs that takes advantage of the FPGA architecture to save FPGA resources if this precision is sufficient.
Cyclone V devices use ALMs instead of LEs (one ALM is approximately two LEs plus two registers) and DSP blocks instead of multipliers (one DSP block can implement two 18-bit multipliers or other functions).
The results show:
- 26-bit floating-point precision uses fewer resources because datapaths are narrower and simpler with reduced precision.
- Fixed-point designs use significantly fewer resources than floating-point designs. Typically, implement fixed-point designs if you do not require the high dynamic range that floating-point offers. However, floating-point designs avoid arithmetic overflow during algorithm development and tuning.
- Fixed-point designs can achieve a processing latency down to 0.1 μs, which is ideal for designs that require very high update frequencies.
- Folded designs use significantly fewer resources than designs without folding. Folding increases latency to around 1 μs, which is still acceptable for the control loop.
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