AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
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9.9.5. DSP Builder for Intel FPGAs Model Resource Usage

For the Drive-On-Chip Design, Intel compared the FOC algorithm as a single precision floating-point model to a model that uses the folding feature. When you use folding, the model uses fewer logic elements (LEs) and multipliers but has an increase in latency. In addition, a fixed-point model uses significantly fewer LEs and multipliers and has lower latency than the floating-point model.

Intel compared floating- and fixed-point versions of the FOC algorithm with and without folding. In addition, Intel compared using a 26-bit (17-bit mantissa) instead of standard single-precision 32-bit (23-bit mantissa) floating point implementation. 26-bit is a standard type within DSP Builder for Intel FPGAs that takes advantage of the FPGA architecture to save FPGA resources if this precision is sufficient.

Cyclone V devices use ALMs instead of LEs (one ALM is approximately two LEs plus two registers) and DSP blocks instead of multipliers (one DSP block can implement two 18-bit multipliers or other functions).

Table 19.  Resource Usage Comparison for Cyclone V Devices
Design Folding Precision ALMs DSPs Latency (us) M10K
Floating-point No 32 9968 31 0.99 19
Floating-point Yes 32 3840 4 1.77 1
Floating-point No 26 8995 31 0.99 15
Floating-point Yes 26 3634 4 1.75 3
Fixed-point No 16 1979 24 0.22 2
Fixed-point Yes 16 2510 1 1.99 2

The results show:

  • 26-bit floating-point precision uses fewer resources because datapaths are narrower and simpler with reduced precision.
  • Fixed-point designs use significantly fewer resources than floating-point designs. Typically, implement fixed-point designs if you do not require the high dynamic range that floating-point offers. However, floating-point designs avoid arithmetic overflow during algorithm development and tuning.
  • Fixed-point designs can achieve a processing latency down to 0.1 μs, which is ideal for designs that require very high update frequencies.
  • Folded designs use significantly fewer resources than designs without folding. Folding increases latency to around 1 μs, which is still acceptable for the control loop.