AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

9.10. FFTs

FFT0 and FFT1 correspond to the two 4,096pt FFT blocks that the design implements on the SoC for vibration suppression. The design provides two FFTs to enable immediate comparison between the FFTs of different internal control signals. Each calculates an FFT on the last 4,096 samples input to it. The number of samples between each new calculation is configurable. The design uses 64 samples between each new calculation, so each new FFT is based on the same data set as the previous one except for 64 new points. Given the sample rate of 16kHz, the design produces new FFT data sets at 250Hz. Thus vibration detection can react quickly, before equipment is damaged.
Figure 49. FFT Overlapping Data Sets

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