9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
The FOC algorithm comprises the FOC algorithm block and a latch block for implementing the integrators necessary for the PI controllers in the FOC algorithm. DSP Builder for Intel FPGAs implements the latches outside because of limitations of the folding synthesis.
The design includes fixed-point and floating-point models that implement the FOC algorithm.
Each model calls a corresponding .m setup script during initialization to set up the arithmetic precision, folding factor, and target clock speed. The folding factor is set to a large value to minimize resource usage.
|Model||Folding Factor||Clock Speed (MHz)||Input Precision||Output Precision|
The following models generate the FOC block including the Avalon memory-mapped interface:
- DFf_float_alu_av.slx for floating-point designs
- DFf_fixp16_alu_av.slx for fixed-point designs
A Simulink* library model contains the main FOC algorithm code, which the other models refer to:
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