AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Document Table of Contents

9.9.2. Avalon Memory-Mapped Interface

The Drive-On-Chip Design DSP Builder for Intel FPGAs-generated VHDL has a signal interface that matches the connections in Simulink*. Feedback currents, position feedback, torque command, and gain parameters are all parallel inputs into the system and voltage commands are parallel outputs.

To allow direct connectivity in Qsys, the top-level DSP Builder for Intel FPGAs design adds blocks to terminate the parallel inputs and outputs and handshaking logic with an Avalon memory-mapped register map.

Figure 47. FOC Model integrated in Simulink* with Avalon-MM Register Map

DSP Builder for Intel FPGAs generates a .h file that contains address map information for interfacing with the DSP Builder for Intel FPGAs model.

To run the DSP Builder for Intel FPGAs model as part of the drive algorithm, a C function passes the data values between the processor and DSP Builder for Intel FPGAs. The handshaking logic ensures synchronization between the software and hardware. The software sets up any changes to hardware parameters such as PI gains, writes new feedback currents, position feedback and torque command input data before starting the DSP Builder for Intel FPGAs calculation. The software then waits for the DSP Builder for Intel FPGAs calculation to finish before reading out the new voltage command data.

The ISR that runs the FOC algorithm calls the C function with an option to switch between software and DSP Builder for Intel FPGAs implementations at runtime.

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