7.3. Scale Factors for the Drive-On-Chip Design Example in the System Console Toolkit
|Item||Sigma Delta Scaling|
|Motor Phase Voltages||545 counts/A|
|DC Bus Voltage||545 counts/V|
|Input Voltage||895 counts/V|
|Input Current||252 counts/A|
|Inductor Current||717 counts/A|
|DC Bus Current||1638 counts/A|
|Motor Phase Currents||1.024 counts/mA|
|Item||Sigma Delta Scaling (counts/mA)|
|Id Direct Current||1.024|
|Iq Quadrature Current||1.024|
The design calculates the maximum count of the PWM from the PWM clock frequency. The maximum count varies with the PWM clock frequency and sample rate and is (PWM frequency in Hz)/( (Sample rate) *1000). For example, with a PWM clock frequency of 300 MHz and a sample rate of 16 kHz the maximum count is 18,750.
Voltage demand signals for the PWM IP have a full-scale value equal to the maximum count, so setting the voltage demand to the maximum count value achieves 100% duty cycle and 100% of DC link voltage. Setting the voltage demand to 0 achieves 0% duty cycle and 0% of the DC link voltage. By convention, voltages for display purposes are centred around 0. For example, if the DC link voltage is 48 V voltage demand signals between 0 and maximum count map to 0 to +48 V outputs, but these signals are offset and show in System Console as -24 V to +24 V.
Using the above example of 300 MHz PWM and 16 kHz sample rate for the Tandem Motion-Power 48 V Board, in System Console:
Offset 18,750/2 = 9,375
Scaling 9,375/24 = 391
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