AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

9.9.4. DSP Builder for Intel FPGAs Folding

DSP Builder for Intel FPGAs generates flat parallel models that can receive and process new input data on every clock pulse. However, designs that have a much lower sample rate than the FPGA clock rate, such as this FOC design (16 kHz versus 100 MHz), can use the DSP Builder for Intel FPGAs folding feature to trade off an increase in algorithm latency for a decrease in the FPGA resources. This feature allows the design to use as much hardware parallelism as necessary to reach the target latency with the most cost-effective use of FPGA resources without making any changes to the algorithm.

The DSP Builder for Intel FPGAs folding feature reuses physical resources such as multipliers and adders for different calculations with the VHDL generation automatically handling the complexity of building the time division multiplexed (TDM) hardware.

Figure 48. Unfolded and Folded Hardware Examples

Did you find the information on this page useful?

Characters remaining:

Feedback Message