AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

9. Functional Description of the Drive-On-Chip Design Example

The design consists of two main elements: Qsys, DSP Builder for Intel FPGAs, IP, and RTL sources compiled into an FPGA programming file; and C source code compiled to run on an Arm Cortex-A9 in the HPS in the FPGA.
Figure 26. Block Diagram for Cyclone V SoC Development Board

The Qsys system consists of:

  • Processor subsystem
  • DC link monitors
  • DC-DC converter
  • FOC subsystem
  • FFTs
  • Two motor drive axes comprising the following motor control peripheral components:
    • 6-channel PWM
    • Drive system monitor
    • Quadrature encoder interface
    • Resolver SPI interface
    • ADC interface
Figure 27. Qsys System Top-Level Design
Figure 28. Qsys System for a Drive Axis
Figure 29. Qsys System for DC-DC Converter

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