AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

9.12. Signals

The signals connect various blocks in the Drive-On-Chip Design Example.
Table 23.  Six-Channel PWM Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input PWM and system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
pwm_enable Input PWM enable from drive system monitor
en_upper Input Upper switch enable from drive system monitor
en_lower Input Lower switch enable from drive system monitor
u_h Output Motor phase U upper gate drive
u_l Output Motor phase U lower gate drive
v_h Output Motor phase V upper gate drive
v_l Output Motor phase V lower gate drive
w_h Output Motor phase W upper gate drive
w_l Output Motor phase W lower gate drive
sync_in Input Synchronization signal for multiple PWM modules
sync_out Output Synchronization signal for multiple PWM modules
start_adc Output ADC start conversion signal
Table 24.  DC Link Monitor Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
clk_adc Input ADC clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
avs_irq Output Avalon interrupt
Conduit Signals
sync_dat Input Sigma-delta ADC bit stream
dc_link_enable Input Enable
overvoltage Input Overvoltage status
undervoltage Output Undervoltage status
chopper Output Chopper circuit gate drive
Table 25.  Drive System Monitor Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
overcurrent Input Overcurrent status
overvoltage Input Overvoltage status
undervoltage Input Undervoltage status
chopper Input Chopper status
dc_link_clk_err Input Clock monitor status
igbt_err Input IGBT error status
error_out Output Error output
overcurrent_latch Output Latched overcurrent status
overvoltage_latch Output Latched overvoltage status
undervoltage_latch Output Latched undervoltage status
dc_link_clk_err_latch Output Latched clock monitor status
igbt_err_latch Output Latched IGBT error status
chopper_latch Output Latched chopper status
pwm_control[2:0] Output PWM control
Table 26.  Quadrature Encoder Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
strobe Input Capture strobe
QEP_A Input Quadrature phase A
QEP_B Input Quadrature phase B
QEP_I Input Quadrature index
Table 27.  Sigma-Delta ADC Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
clk_adc Input ADC clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
avs_irq Output Interrupt request
Conduit Signals
start Input Start conversion signal
sync_dat_u Input Phase U sigma-delta bitstream
sync_dat_v Input Phase V sigma-delta bitstream
sync_dat_w Input Phase W sigma-delta bitstream
overcurrent Output Overcurrent status
Table 28.  FFT IP
SignalName Direction Description
Avalon Memory-Mapped Interface Signals
clk Input FPGA system clock input
areset Input System reset signal, active high
h_areset Input Reset signal for Avalon memory-mapped interface, active high
busIn_read Input Avalon memory-mapped read strobe, active high
busIn_write Input Avalon memory-mapped write strobe, active high
busIn_address[5:0] Input Avalon memory-mapped address bus
busIn_writedata[31:0] Input Avalon memory-mapped write data bus
busOut_readdata[31:0] Output Avalon memory-mapped read data bus
busOut_readdatavalid Output Avalon memory-mapped read data valid
Conduit Signals for FFT results output
qreal[31:0] Output FFT output real part
qimag[31:0] Output FFT output imaginary part
exponent[4:0] Output Exponent of FFT output real/imaginary part
busy_fft Output FFT processing busy flug, active high
exp_error Output Error flag, active high
qv_fft Output FFT output data valid
Table 29.  FFT buffer
Signal Name Direction Description
Avalon memory-mapped buffer memory interface signals
avs_clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon memory-mapped read strobe, active low
avs_write_n Input Avalon memory-mapped write strobe, active low
avs_address[11:0] Input Avalon memory-mapped address bus
avs_writedata[63:0] Input Avalon memory-mapped write data bus
avs_readdata[63:0] Output Avalon memory-mapped read data bus
avs_bytenable[7:0] Input Avalon memory-mapped byte enable
Avalon memory-mapped control and status agent interface signals
avalon_csr_slave_read Input Avalon memory-mapped CSR slave read strobe, active high
avalon_csr_slave_readdata[31:0] Output Avalon memory-mapped CSR slave read data
avalon_csr_slave_write Input Avalon memory-mapped CSR slave write strobe, active high
avalon_csr_slave_writedata[31:0] Input Avalon memory-mapped CSR slave write data
Conduit Signals for FFT result data input
dspba_export_qreal_exp [31:0] Input FFT Output real part
dspba_export_qimag_exp [31:0] Input FFT output imaginary part
dspba_export_exponent_exp [4:0] Input Exponent of FFT output real/imaginary part
dspba_export_busy_fft_exp Input FFT processing busy flug, active high
dspba_export_exp_error_exp Input Error flag, active high
dspba_export_qv_fft_exp Input FFT output data valid
Table 30.  DC-DC Converter Interface Signals
Signal Name Direction Description
Avalon memory-mapped interface signals
avs_clk Input 10MHz clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[4:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM read data bus
avs_readdata[31:0] Output Avalon-MM write data bus
Conduit Signals
enable_in Input Enable input
bidir_en_n Input Bidirectional conversion enable
fault Input Fault input. If the design asserts the fault input, it clears the enable bit of the control register, and turns off the DC-DC converter. The design keeps the enable bit clear, and does not set again, until the fault input is negated.
pwm_sync_n Input Synchronization signal
gate_a_h Output Phase 0 upper transistor gate drive
gate_a_l Output Phase 0 lower transistor gate drive
gate_b_h Output Phase 1 upper transistor gate drive
gate_b_l Output Phase 1 lower transistor gate drive
dc_dc_on Output DC-DC status
overvoltage Output Overvoltage error
overcurrent Output Overcurrent error
timeout_latch Output Sample timeout
sync_dat_i_pase_a Input Phase 0 current feedback sigma-delta bitstream
sync_dat_i_pase_b Input Phase 1 current feedback sigma-delta bitstream
sync_dat_v_out Input Voltage feedback sigma-delta bitstream
clk_adc Input ADC clock input

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