9.9.3. About DSP Builder for Intel FPGAs
After you develop the algorithm in Simulink*, DSP Builder can automatically generate pipelined HDL that it targets and optimizes to the chosen FPGA device. You can use this VHDL in a HDL simulator such as ModelSim* to verify the generated logic versus Simulink* and in the Quartus Prime software to compile the hardware. DSP Builder for Intel FPGAs gives instant feedback of the VHDL's logic utilization and algorithm latency in automatically generated Simulink* reports.