AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

9.9.6. DSP Builder for Intel FPGAs Design Guidelines

Use these design guidelines to reduce FPGA resource usage with folding.

In your design:

  • Use the variable precision support in DSP Builder for Intel FPGAs. Instead of using a 32-bit datapath, investigate the algorithm and reduce the numeric format as much as possible. Also keep sufficient accuracy to represent the range of allowed data values.
  • Use components that use fewer FPGA resources. For example, sin(x) and cos(x) blocks require a range reduction stage. Use the smaller sin(pi*x) and cos(pi*x).
  • Use fewer different components to enable resource reuse. For example, restructure a sin(pi*x) and a cos(pi*x) into a sin(pi*x) and sin(pi*(0.5-x)).
  • Ensure that the select line of a multiplexer does not use more bits than necessary. For example, for a 2:1 multiplexer, the select line should be 1 bit.

Did you find the information on this page useful?

Characters remaining:

Feedback Message