AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

7.1. Signal Sensing in Sigma-Delta ADCs

Sigma-delta modulators on the power board convert analog signals to a one-wire digital bitstream. The design demodulates or filters the bitstream in the FPGA. The FPGA uses several types of sigma-delta filter IP in the FPGA, ADC modules and DC link modules, each with different scaling and offset.

The design downloads and filters all sigma delta inputs in parallel so no skew exists between the samples that it feeds to the software application.

Each ADC type has a different input ranges. The corresponding 'C' data type is 16-bit integer.

Table 6.  ADC Output Data
ADC Type Input Range Count Range C Data type
Sigma-delta ADC -320…+320mV -32768…+32767 Signed 16-bit
Sigma-delta DC link voltage 0…+320mV 0…+32767 Signed or unsigned 16-bit

Position feedback samples are scaled to a 23 bit unsigned integer, for consistency across all encoder types supported by this and previous Drive-On-Chip designs.

Table 7.  ADC ScalingThis table shows the ADC scaling for all signals, ADC type and board revision. The scaling depends on the way the power board processes the signals (e.g., value of current shunts, scaling, and offset in sense amplifiers).
Feedback Quantity Sigma Delta Interface IP Sigma Delta Scaling for Tandem Motion Power Board
Motor Phase Voltages ADC interface 545 counts/V
DC Bus Voltage ADC interface 40 counts/V
Input Voltage DC Link 895 counts/V
Input Current DC Link 256 counts/A
DC-DC Inductor Current ADC interface 717 counts/A
DC Bus Current DC Link 1638 counts/A
Motor Phase Currents ADC interface 1024 counts/A
Table 8.  ADC ScalingThis table shows the ADC scaling for all signals. The scaling depends on the way the power board processes the signals (e.g., value of current shunts, scaling, and offset in sense amplifiers) and filter IP scaling in FPGA. The design uses the DC Bus Voltage and DC-DC Inductor Current as feedback control for the DC-DC controller IP, but scales them differently for the DC-DC controller IP. The design performs the scaling in hardware. The table shows the scaling factor in the last column in the table. For more information, refer to DC-DC Control Block.
Feedback Quantity Sigma Delta Interface IP Scaling for Software Interface (Avalon Memory-mapped Registers) Scaling for DC-DC Controller Hardware IP
Motor Phase Voltages ADC interface in DOC_Axix_Periphs subsystem 545 counts/V N/A
Motor Phase Currents ADC interface in DOC_Axix_Periphs subsystem 1024 counts/A N/A
DC link Input Voltage DC Link Monitor in lvmc_dclink subsystem 895 counts/V N/A
DC link input Current DC Link Monitor in lvmc_dclink subsystem 256 counts/A N/A
DC link output (DC Bus) Current DC Link Monitor in lvmc_dclink subsystem 1638 counts/A N/A
DC link output (DC Bus) Voltage ADC interface in DC-DC Boost Converter 545 counts/V 40 counts/V
DC-DC Inductor Currents ADC interface in DC-DC Boost Converter 717 counts/A 100 counts/A

Did you find the information on this page useful?

Characters remaining:

Feedback Message