AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

9.10.1. Servo FFTs

The design uses two parallel instantiations of the DSP Builder Advanced Blockset servo FFT. The servo FFT is a folded FFT design that uses minimal FPGA resources but sufficient performance for typical industrial drive applications.
Table 20.  FFT Resource Usage
Device Logic Memory Other
Cyclone V 550 ALMs 29 M9K 2 DSP blocks

The processing time with a 100-MHz clock is around 0.6ms including the time to clock data out of the FFT block again. The processing time for two parallel FFTs is the same. You may choose other FFT implementations for the FPGA for faster processing times if required, at the expense of FPGA resources.

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