MAX® II and MAX CPLD Design Examples



The examples shown in Tables 1 through 5 demonstrate various features of the MAX II and MAX low-power CPLD families using Quartus® II or MAX+PLUS® II software. For more information about the different design entry methods, refer to the help files in Quartus II or MAX+PLUS II software.

These design examples are intended only for Intel® FPGA devices. The examples are provided on an "as-is" basis and come with no warranties.

Each design example in Tables 1 through 3 includes the following:

  • Source code in Verilog
  • Testbench in Verilog
  • Quartus II Web Edition software version version 6.0 project files and program files for the MDN B2 or MDN B3 demonstration board (the logic element (LE) and I/O resources shown in Tables 1 through 3 are derived from design compilations using Quartus II software version 7.2)
  • ModelSim* 6.1d Web Edition software project file with testbench, wave image files
    • Simulation file not included for large simulations
  • Documentation

Additional examples are available on the Intel® FPGA Design Examples page.