VHDL: Instantiating a D Flipflop using lpm_dff

This example instantiates an 8-bit-wide D flipflop using the lpm_dff function. The Port Map maps the pins in this instance of the function to the correspnding ports in the Component Instantiation Statement for the lpm_dff function, which is contained in the lpm_component package. For more information on using this example in your project, go to:


testdff.vhd

LIBRARY ieee, lpm;
USE ieee.std_logic_1164.ALL;
USE lpm.lpm_components.ALL;

ENTITY testdff IS  
    PORT (inputs : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          clk  : IN STD_LOGIC;
          aset : IN STD_LOGIC ;
          aclr : IN STD_LOGIC ;
          sset : IN STD_LOGIC ;
          sclr : IN STD_LOGIC ;
          en   : IN STD_LOGIC ;
          outputs : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END testdff;

ARCHITECTURE dff8 OF testdff IS
BEGIN
    U1 : lpm_ff 
            GENERIC MAP(lpm_width => 8)
                PORT MAP(data => inputs, 
                clock => clk,q => outputs,         
                aclr => aclr, enable => en, 
                aset => aset, sset => sset,
                sclr => sclr);
END;

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