VHDL: Instantiating a DFFE
This example instantiates a
D flipflop with an
enable signal (DFFE).
The section that is commented out uses the same logic, except the
IF enable statement is switched. The commented section will not synthesize correctly in MAX+PLUS® II because the
enable input will feed both the
enable on the flipflop and added combinatorial logic that then feeds the
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- How to Use VHDL Examples
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ENTITY simpsig IS PORT( enable : IN BIT; d, clk : IN BIT; q : OUT BIT ); END simpsig; ARCHITECTURE maxpld OF simpsig IS BEGIN PROCESS(clk) BEGIN IF (enable = '0' ) then null; ELSIF (clk'event and clk = '1') then q <= d; END IF; END PROCESS; END maxpld; -- The following implementation is incorrect. -- PROCESS(clk) -- BEGIN -- IF (clk'event AND clk = '1') THEN -- IF (enable = '1' ) THEN -- q <= d; -- END IF; -- END IF; -- END PROCESS; -- END maxpld;
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