VHDL: Ripple-Carry Adder

This example illustrates the use of the For Generate statement to construct a ripple-carry adder from a full adder function. It also shows how to use a package definition in the usr_def.vhd design file. Note that the file usr_def.vhd calls a full adder from the full_add.vhd file. Also note that usr_def.vhd must be compiled before f_add8.vhd is compiled. The ripple-carry adder shown in this example can be used in designs where the efficient use of logic resources is more important than design performance.

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f_add8.vhd

LIBRARY altera;
USE altera.maxplus2.carry;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

LIBRARY WORK;
USE WORK.usr_def.ALL;

ENTITY f_add8 IS    
    PORT(
        x_in    :    IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        y_in    :    IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        c_in    :    IN STD_LOGIC;
        sum     :    OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        c_out   :    OUT STD_LOGIC);
END f_add8;

ARCHITECTURE struct OF f_add8 IS
SIGNAL im  :    STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL imi :    STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
    c0   : full_add 
           PORT MAP (x_in(0),y_in(0),c_in,sum(0),im(0));
    c01  : carry 
           PORT MAP (im(0),imi(0));
    c    : FOR i IN 1 TO 6 GENERATE
            c1to6:  full_add PORT MAP (x_in(i),y_in(i),
            imi(i-1),sum(i),im(i));
            c11to16: carry PORT MAP (im(i),imi(i));
           END GENERATE;
    c7   : full_add PORT MAP (x_in(7),y_in(7),
           imi(6),sum(7),c_out);
END struct;

usr_def.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE usr_def IS
   COMPONENT full_add 
      PORT(
          a      : IN STD_LOGIC;
          b      : IN STD_LOGIC;
          c_in   : IN STD_LOGIC;
          sum    : OUT STD_LOGIC;
          c_out  : OUT STD_LOGIC);
   END COMPONENT;
END usr_def;

full_add.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY full_add IS 
    PORT(
        a     : IN    STD_LOGIC;
        b     : IN    STD_LOGIC;
        c_in  : IN    STD_LOGIC;
        sum   : OUT   STD_LOGIC;
        c_out : OUT   STD_LOGIC);
END full_add;

ARCHITECTURE behv OF full_add IS
BEGIN
    sum <= a XOR b XOR c_in;
    c_out <= (a AND b) OR (c_in AND (a OR b));
END behv;

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