This example is a 4-bit down counter with a synchronous set. This example shows two different methods for mapping the
lpm_counter function. The second method, which is commented out in the example, maps all of the ports on the
lpm_counter. MAX+PLUS® II will synthesize out the unused connections.
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LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; --Allows use of all Altera LPM USE lpm.lpm_components.all; --functions ENTITY cnt_3 IS PORT (clock : IN STD_LOGIC; sset : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END cnt_3; ARCHITECTURE lpm OF cnt_3 IS BEGIN -- Port map 1 U1: lpm_counter GENERIC MAP (lpm_width => 4, lpm_direction => "down") PORT MAP (clock => clock, sset => sset, q => q); -- Port map 2 -- -- PORT MAP (data => "0000", clock => clock, clk_en => '1', -- cnt_en => '1', updown => '0', sload => '0', -- sset => SSET, sclr => '0', aload => '0', -- aset => '0', aclr => '0', q => q); -- These portmaps will produce the same results. -- The second portmap has more connections but -- the extraneous connections will be synthesized out. END;
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