Interface protocols enable chip-to-chip, board-to-board, or box-to-box connectivity in system designs. Protocol intellectual property (IP) solutions from Intel FPGA and our partners satisfy the needs of a broad spectrum of applications and leverage the integrated transceivers in our FPGA and ASIC devices. Interface protocol solutions are delivered as licensable IP cores and reference designs as well as no-cost megafunctions and design examples.
Visit our Transceiver Protocols section to learn more about the integrated transceivers and their supporting interface protocol solutions.
Designs targeted for the Intel MAX 10 FPGA device family and its development kits are available in the new Design store.
Design Examples | Device Targeted | Development Kits Supported | Qsys Compliant | Quartus II Version |
---|---|---|---|---|
GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs: AN 494 (PDF) |
MAX II | - | - | - |
I2C Battery Gauge Interface Using MAX II CPLDs: AN 493 (PDF) |
MAX II | - | - | - |
MAX II | - | - | 10 | |
MAX II | - | - | - | |
Cyclone III | Intel FPGA Embedded Systems Development Kit, Cyclone III Edition | - | 9.1 | |
RapidIO: Maintenance Host to System Maintenance Agent Bridge |
- | - | - | All |
Serial Peripheral Interface (SPI) Host in MAX II CPLDs: AN 485 (PDF) |
MAX II | - | - | 7.2 |
MAX II | MDN-B2 | - | - | |
MAX II | - | - | - | |
MAX II | - | - | 10 | |
MAX II | MDN-B2 | - | 7.2 |