This design example demonstrates how to use the SPI Slave to Avalon® Master Bridge to provide a connection between the host and the remote system for SPI transactions.
The system in this design example consists of two sub-systems. The first is the host system, which consists of a Nios® II CPU and SPI Master Core, that initiates the SPI transactions. The second is the remote system which consists of the SPI Slave to Avalon Master Bridge and an on-chip memory. For demonstration purposes, these two sub-systems are connected internally within the FPGA without going through any physical pin routing.
The software portion demonstrates how to perform read and write transactions using the SPI Slave to Avalon Master Bridge. In order for the SPI Slave to Avalon Master Bridge to successfully convert incoming streams of data into Avalon Memory-Mapped (Avalon-MM) transactions, the host system CPU needs to encode and packetize the streams of data according to the protocols used by the bridge. Similarly, outgoing streams of data from the SPI Slave to the Avalon Master Bridge need to be converted according to the same protocol used by the CPU. The software files needed to perform this process are included in the ZIP file.
This design example is an updated version of Embedded Systems Development Kit , Cyclone III Edition and is targeted to be used with Cyclone V SoC developement kit.
Figure 1. SPI Slave to Avalon Master Bridge Design Example Block Diagram
Hardware Design Specifications
- Nios II/f
- On-chip memory: 156K
- System timer
- System ID
- JTAG UART
- SPI Core
- SPI Slave to Avalon Master Bridge
- On-chip memory: 4K
Download the files used in this example:
For Cyclone V SoC :
Note: This link directs you to the design store to download the design example and quick reference guide document which includes the instructions for running the design.
For Cyclone III:
Note: The .zip file contains all the necessary hardware and software files to reproduce this example. The readme.txt file includes instructions for running the design.
The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.
Design Example Disclaimer
This design example may only be used within Intel devices and remain the property of Intel Corporation. It is being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.