|Introduces the basic features, files, and design flow of the Intel Quartus Prime Pro Edition software, including managing Intel Quartus Prime Pro Edition projects and intellectual property (IP), initial design planning considerations, and project migration from previous software versions.
|Describes how to create and optimize systems using the Platform Designer, a system integration tool that simplifies integrating customized IP cores in your project. The Platform Designer automatically generates interconnect logic to connect IP functions and subsystems.
|Describes best design practices for designing FPGAs with the Intel Quartus Prime Pro Edition software. HDL coding styles and synchronous design practices can significantly impact design performance. Following recommended HDL coding styles ensures that the Intel Quartus Prime Pro Edition software synthesis optimally implements your design in hardware.
|Describes how to set up, run, and optimize for all stages of the Intel Quartus Prime Pro Edition software compiler. The compiler synthesizes, places, and routes your design before generating a device programming file.
|Describes the Intel Quartus Prime Pro Edition software settings, tools, and techniques that you can use to achieve the highest design performance in Intel® FPGAs. Techniques include optimizing the design netlist, addressing critical chains that limit retiming and timing closure, and optimization of device resource usage.
|Describes operation of the Intel Quartus Prime Pro Edition software programmer, which allows you to configure Intel FPGAs, and program CPLD and configuration devices via connection with an Intel FPGA Download Cable.
|Describes block-based design flows, also known as modular or hierarchical design flows. These advanced flows enable preservation of design blocks (or logic that comprises a hierarchical design instance) within a project, and reuse of design blocks in other projects.
|Describes Partial Reconfiguration, an advanced design flow that allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Define multiple personas for a particular design region without impacting operation in other areas.
|Describes RTL- and gate-level design simulation support for third-party simulation tools by Aldec*, Cadence*, Mentor Graphics*, and Synopsys* that allow you to verify design behavior before device programming. Includes simulator support, simulation flows, and simulating Intel FPGA IP.
|Describes support for optional synthesis of your design in third-party synthesis tools by Mentor Graphics and Synopsys. Includes design flow steps, generated file descriptions, and synthesis guidelines.
|Describes a portfolio of Intel Quartus Prime Pro Edition software in-system design debugging tools for real-time verification of your design. These tools provide visibility by routing (or “tapping”) signals in your design to debugging logic. These tools include System Console, Signal Tap logic analyzer, Transceiver Toolkit, In-System Memory Content Editor, and In-System Sources and Probes Editor.
|Explains basic static timing analysis principals and use of the Intel Quartus Prime Pro Edition software Timing Analyzer, a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology.
|Power Analysis and Optimization
|Describes the Intel Quartus Prime Pro Edition software Power Analysis tools that allow accurate estimation of device power consumption. Estimate the power consumption of a device to develop power budgets and design power supplies, voltage regulators, heatsink, and cooling systems.
|Describes timing and logic constraints that influence how the compiler implements your design, such as pin assignments, device options, logic options, and timing constraints. Use the Interface Planner to prototype interface implementations, plan clocks, and quickly define a legal device floorplan. Use the Pin Planner to visualize, modify, and validate all I/O assignments in a graphical representation of the target device.
|PCB Design Tools
|Describes support for optional third-party PCB design tools by Mentor Graphics and Cadence. Also includes information about signal integrity analysis and simulations with HSPICE and IBIS models.
|Describes use of Tcl and command line scripts to control the Intel Quartus Prime Pro Edition software and to perform a wide range of functions, such as managing projects, specifying constraints, running compilation or timing analysis, or generating reports.