External Memory Interfaces IP Support Center

The External Memory Interface (EMIF) support page will help you find information regarding Intel Agilex® 7, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 FPGAs on how to plan, design, implement, and verify your external memory interfaces. You will also find debug, training, and other resource materials on this page.

This page is set up to walk you through the design process from start to finish.

For support resources regarding other FPGAs, search within the following links: FPGA Documentation Index, Training Courses, Videos, Design Examples, and Knowledge Base.

Getting Started

1. Device Selection

How Do I Select a Device?

Two tools are available to help you select an Intel® FPGA based on your memory requirements:

How Do I Select an External Memory Intellectual Property (IP)?

To learn about the various memory intellectual property (IP) available, refer to the following online training curriculum:

2. User Guides and Documentation

Intel Agilex 7 Devices

EMIF IP User Guide

• External Memory Interfaces Intel Agilex® 7 FPGA IP User Guide

Design Example User Guide

• External Memory Interfaces Intel Agilex® 7 FPGA IP Design Example User Guide

Release Notes

• External Memory Interfaces Intel Agilex® 7 FPGA IP Core Release Notes

Pin-Out Files

• Intel Agilex device pin-out and EMIF address/command pin out

Intel Stratix 10 Devices

EMIF IP User Guide

• External Memory Interfaces Intel Stratix 10 FPGA IP user guide

Design Example User Guide

• External Memory Interfaces Intel Stratix 10 FPGA IP Design Example user guide

Release Notes

• External Memory Interfaces Intel Stratix 10 FPGA IP Core release notes

Pin-Out Files

• Intel Stratix 10 device pin-out and EMIF address/command pin-out

Intel Arria 10 Devices

EMIF IP User Guide

• External Memory Interfaces Intel Arria 10 FPGA IP user guide

Design Example User Guide

• External Memory Interfaces Intel Arria 10 FPGA IP Design Example user guide

Release Notes

• Intel Arria 10 FPGA IP Core release notes

Pin-Out Files

• Intel Arria 10 device pin-out and EMIF address/command pin-out

Intel Cyclone 10 Devices

EMIF IP User Guide

• External Memory Interfaces Intel Cyclone 10 GX FPGA IP user guide

Design Example User Guide

• External Memory Interfaces Intel Cyclone 10 GX FPGA IP Design Example user guide

Release Notes

• External Memory Interfaces Intel Cyclone 10 FPGA IP Core release notes

Pin-Out Files

• Intel Cyclone 10 device pin-out and EMIF address/command pin-out

Intel FPGA PHY Lite

• PHY lite for Parallel Interfaces Intel FPGA IP Core user guide

Intel FPGA HBM2 User Guide

• High Bandwidth Memory (HBM2) Interface Intel FPGA IP user guide

3. EMIF IP Generation

Where Do I Find Information on the EMIF IP?

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following External Memory Interfaces IP User Guides:

• Please refer to 'User Guides' Section

How Do I Generate the EMIF IP?

For detailed information regarding External Memory Interface (EMIF) Intellectual Property (IP) parameters, refer to the following protocol-specific sections within the following EMIF IP User Guides:

Note: For more information on 'How Do I Generate IP', refer to the 'User Guide' and 'Training Course and Video' sections.

How Do I Perform Functional Simulation?

For detailed information on simulating the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following section within the EMIF IP User Guides:

• Intel Agilex® 7 FPGA EMIF IP – Simulating Memory IP
• Intel Stratix 10 simulating Memory IP
• Intel Stratix 10 MX simulating HBM2 IP
• Intel Arria 10 simulating Memory IP
• Intel Cyclone 10 simulating Memory IP

For instructions on how to generate an EMIF simulation design example and how to run simulations using the ModelSim*-Intel FPGA simulation software, refer to the following sections within the EMIF IP Design Example User Guides:

• Intel Agilex® 7 FPGA - Generating the EMIF Design Example for Simulation
• Intel Stratix 10 generating the EMIF design example for simulation
• Intel Arria 10 generating the EMIF design example for simulation
• Intel Cyclone 10 generating the EMIF design example for simulation

For information on how to verify an EMIF design, refer to the 'Training Courses and Video' section for the 'Verifying Memory Interfaces IP' course.

Where Do I Find Information on FPGA Resource and Pin Placement?

For detailed External Memory Interface (EMIF) pin information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

For simplified I/O placement refer to the Interface Planner for an easy-to-use drag-and-drop tool available in the Intel Quartus Prime Pro Edition software for Intel Arria 10 and Intel Stratix 10 FPGAs. Refer to the following videos for information on how to use the Interface Planner and its benefits:

• Interface planner for EMIF video (Part 1)
• Interface planner for EMIF video (Part 2)

For more information on Interface Planner for resource location assignments, refer to the following online training curriculum:

Additional Resources

What is Ping Pong PHY?

Ping Pong PHY allows two memory interfaces to share Address and Command buses. This is supported for DDR3 and DDR4 protocols and for Stratix® V, Intel Arria 10, and Intel Stratix 10 FPGAs. Refer to the following video for information on the concept of Ping Pong PHY, its benefits, and an analysis of simulation results:

• DDR4 Ping Pong PHY video

Where Do I Find Information on PHYLite?

ThePHYLite IP allows you to build custom memory interface PHY blocks for Intel Arria 10 and Intel Stratix 10 FPGAs. For detailed information about the PHYLite IP, refer to the following user guide:

• PHYLite for Parallel Interfaces IP Core user guide

For detailed information on how to properly assign pinouts for PHYLite based on different DQ/DQS group sizes, refer to the following video:

• PHYLite group pin placement video (Note: The video is also applicable to Intel Stratix 10 devices.)

The PHYLite IP supports many different I/O standards and termination values on input and output buffers for Intel Arria 10 and Intel Stratix 10 FPGAs. Refer to the following video for information on how to create an On-Chip-Termination (OCT) block and how to associate it with the terminated I/O buffer in the PHYLite IP:

• OCT block for PHYLite video

Where Do I Find Information on Board Layout and Design?

For detailed External Memory Interface (EMIF) board layout and design information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

How Do I Perform Board/Channel Simulation?

For information on measuring write-and-read Intersymbol Interference (ISI) and Crosstalk, arranging Command, Address, Control and Data pins, and I/O bank placement restrictions, refer to the following guidelines:

• Intel Arria 10 device channel simulation guidelines
• Calculating channel loss from DDRx simulation guidelines (Note: The Intel Arria 10 channel guidelines is also applicable to Intel Stratix 10 devices)

Where Do I Find Information on Timing Closure?

For information regarding External Memory Interface (EMIF) timing closure, refer to the following section within the EMIF Intellectual Property (IP) User Guides:

• Intel Agilex® 7 Devices EMIF IP Timing Closure
• Intel Stratix 10 EMIF IP timing closure
• Intel Arria 10 EMIF IP timing closure
• Intel Cyclone 10 EMIF IP timing closure

5. Debug

How Do I Debug My External Memory Interface Design?

For information regarding debugging the external memory interface (EMIF) intellectual property (IP), refer to the following section within the EMIF IP User Guides:

• Intel Agilex® 7 Devices - EMIF IP Debugging
• Intel Agilex® 7 Devices - EMIF Self-Debug Guide Tool
• Intel Stratix 10 EMIF IP debugging
• Intel Arria 10 EMIF IP debugging
• Intel Cyclone 10 EMIF IP debugging

The main tool available for debug is the EMIF Debug Toolkit:

How Do I Use the EMIF Debug Toolkit?

For step-by-step instructions on how to daisy-chain multiple memory interfaces for compatibility with the EMIF Debug Toolkit, refer to the following user guide:

• Debugging Multiple Memory Interfaces guide

The Read/Write 2-D Eye Diagram feature available in the EMIF Debug Toolkit generates read-and-write eye diagrams for each data pin. Refer to the following video for information on important voltage reference parameters during the EMIF IP generation process and how to use the 2-D Eye Diagram feature:

• 2-D Eye diagram video

The Traffic Generator 2.0 allows you to test and debug your external memory interface through customizable traffic and test patterns. Refer to the following guide and videos for detailed information on how to use the Traffic Generator 2.0 feature:

• Traffic Generator 2.0 guide
• Traffic Generator 2.0 Video (coming soon)

The Driver Margining feature allows you to capture read-and-write margining data per pin during user-mode traffic. Refer to the following videos for information on the differences between driver margining and calibration margining, and instructions on how to use the Driver Margining feature:

• Driver margining video (Part 1)
• Driver margining video (Part 2)

For information on how to debug an EMIF design, refer to the following online training curriculum:

Where Can I Find Information Regarding Optimizing Controller Performance?

For information regarding controller performance and efficiency, refer to the following section within the External Memory Interfaces (EMIF) Intellectual Property (IP) User Guides:

• Intel Agilex optimizing controller performance
• Intel Stratix 10 optimizing controller performance
• Intel Stratix 10 HBM2 controller performance
• Intel Arria 10 optimizing controller performance
• Intel Cyclone 10 optimizing controller performance

How Do I Learn About Known Issues Regarding EMIF?

For information on current and known issues regarding the EMIF IP, refer to the Knowledge Base:

• Knowledge base for Intel Agilex devices
• Knowledge base for Intel Stratix 10 devices
• Knowledge base for Intel Arria 10 devices
• Knowledge base for Intel Cyclone 10 devices

6. Training Courses and Video

Training Courses

Intel Agilex 7 Device

• Introduction to Memory Interfaces in Intel Agilex® 7 Devices
• Integration of Memory Interfaces in Intel Agilex® 7 Devices
• Verifying Memory Interfaces in Intel Agilex® 7 Devices
• On-Chip debugging of Memory Interfaces in Intel Agilex® 7 Devices

Intel Arria 10 and Intel Stratix 10 Devices

• Introduction to Memory Interfaces IP in Intel Arria 10 and Intel Stratix 10 devices
• Integrating Memory Interfaces IP in Intel Arria 10 amd Intel Stratix 10 devices
• Verifying Memory Interfaces IP in Intel Arria 10 and Intel Stratix 10 devices
• On-Chip debugging of Memory Interfaces IP in Intel Arria 10 and Intel Stratix 10 devices
• High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX devices: implementation

Video

• DDR4 Ping-Pong Phy (devices supported are Stratix V, Intel Arria 10, and Intel Stratix 10)
  
• Introducing BluePrint platform designer for External Memory Interface Design part 1 of 2
• Introducing BluePrint platform designer for External Memory Interface Design part 2 of 2
• How to implement package deskew in External Memory Interface design in Intel Stratix 10 and Intel Arria 10
• Board Timing for Intel Arria 10 EMIF IP
• Implementing over constraint in Intel Arria 10 External Memory Interface
• Automated check of Intel® FPGA External Memory Interfaces board layout guidelines
• How to build RLDRAM3 EMIF design for Intel Arria 10 development kit and test the calibration status using EMIF toolkit
• Intel Arria 10 External Memory Interface toolkit
• Intel Arria 10 EMIF example traffic generator
• Using the Soft Nios® Processor to debug Intel Arria 10 External Memory Interfaces

Still Have Questions?

Comprehensive list of FPGA devices and product collections categorized by product lifecycle stages.

• Intel® FPGA Device and Product Support Collections

Recommended Reading

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following EMIF IP User Guides:

• Intel Stratix 10 External Memory Interfaces IP user guide
• Intel Stratix 10 MX HBM2 IP user guide
• Intel Arria 10 External Memory Interfaces IP user guide
• Intel Cyclone 10 External Memory Interfaces IP user guide
• PHY Lite for Parallel Interfaces Intel® FPGA IP Core user guide

Recommended Training

For training courses on external memory interfaces, refer to the following training catalogs:

• Course catalog