External Memory Interfaces IP Support Center

 

EMIF Device Selector

EMIF Spec Estimator

Features

  • Determines memory interfaces needed to achieve a desired bandwidth
  • Calculates bandwidth based on selected memory configurations
  • Displays all Intel Agilex, Intel Stratix 10, and Intel Arria 10 FPGAs supporting selected memory interfaces
  • Determines performance achievable for specific configuration of the selected Intel FPGA device family
  • Displays maximum frequency for each FPGA family, speed grade and EMIF configuration based on filter selections
  • Find and compare performance of each supported external memory interfaces and configurations for our FPGAs

Device Support

  • Intel Agilex FPGAs
  • Intel Stratix 10 FPGAs
  • Intel Arria 10 FPGAs
  • All Intel FPGAs

Resources

EMIF Tools

Download EMIF device selector tool

Open EMIF spec estimator page

Training Course

Description

Introduction to Memory Interfaces IP in Intel FPGA devices

This course covers the different external memory interface options available, as well as the architectural and hard memory controller features for Intel Stratix 10 and Intel Arria 10 FPGAs

High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX devices: Introduction, Architecture

This course covers the benefits of integrating High Bandwidth Memory into the Intel Stratix 10 MX FPGA devices, features and options for the hardened HBM controller, and how to generate the HBM2 IP

High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX devices: HBMC features

This course covers the features and options for the hardened HBM controller, and the Arm* AMBA 4 AXI interface between the controller and user logic

SoC hardware overview: Interconnect and Memory

This course covers the features of the Hard Processor Subsystem (HPS) SDRAM and the AMBA AXI bridge architecture

 

Intel Agilex

Intel Stratix 10

Intel Arria 10

Intel Cyclone 10

EMIF IP Parameter Descriptions

 

Intel Agilex

Intel Stratix 10

Intel Arria 10

Intel Cyclone 10

EMIF Pin and Resource Planning

Training Course

Description

Fast & Easy I/O system design with interface planner

This course covers how to implement a design resource floorplan using Interface Planner

 

Intel Agilex

Intel Stratix 10

Intel Arria 10

Intel Cyclone 10

EMIF Board Design Guidelines

 

Board Skew Parameter Tool

Channel Loss Calculation Tool

Features

  • Calculates board skew due to PCB traces and multi-rank designs
  • Calculates channel loss due to Intersymbol Interference (ISI) and Crosstalk on Command, Address, Control, and Data signals

Support

  • Intel Arria 10 and Intel Stratix 10 FPGAs
  • DDR memory protocols
  • Compatible with Mentor Graphics HyperLynx Signal Integrity software only

Tools

 

EMIF Debug Toolkit

Features

  • Displays pre and post calibration margins per DQS group and DQ pin
  • Generates read/write eye diagrams per DQ pin (2-D eye diagram)
  • Allows customizable real-time traffic generator for test/debug (Traffic Generator 2.0)
  • Captures read/write margins during user-mode traffic (Driver Margining)

Support

  • Compatible with EMIF design example projects and custom EMIF designs containing one or more memory interfaces
  • Supports all memory protocols

Accessibility

  • Accessible through the Intel Quartus Prime software (Tools > System Debugging Tools > External Memory Interface Toolkit)

Training Course

Description

On-Chip debugging of Memory Interfaces IP in Intel Arria 10 devices

This course covers how to perform debug using the EMIF Toolkit or On-Chip Debug Toolkit, how to use Traffic Generator 2.0, and configure multiple memory interface designs for compatibility with these debug tools