DisplayPort IP Support Center

Feature Description

    DisplayPort IP Core Features

  • Conforms to the Video Electronics Standards Association (VESA) DisplayPort Standard version 2.0
  • Scalable main data link
  • 1, 2, or 4 lane operation
  • 1.62, 2.7, 5.4, 8.1, and 10.0 gigabits per second (Gbps) per lane with an embedded clock (1)(2)
  • Color support
  • RGB 18, 24, 30, 36, or 48 bpp
  • YCbCr 4:4:4 24, 30, 36, or 48 bpp
  • YCbCr 4:2:2 16, 20, 24, or 32 bpp
  • YCbCr 4:2:0 12, 15, 18, or 24 bpp
  • 8B/10B Channel Coding supports 40-bit (quad symbol) and 20-bit (dual symbol) transceiver data interface
  • 128B/132B Channel Coding supports 32-bit transceiver data interface
  • Support for 1, 2, or 4 parallel pixels per clock
  • Support for 2 or 8 audio channels
  • 8B/10B Channel Coding supports Multi-stream transport (MST)
  • Intel Arria® 10 devices support up to 4 streams
  • Intel Cyclone® 10 GX devices support up to 4 streams
  • 128B/132B Channel Coding supports up to 4 streams
  • 8B/10B Channel Coding supports progressive and interlaced video
  • 128B/132B Channel Coding supports progressive video
  • Source support for proprietary video image format (optional)
  • Support for sink non-GPU mode
  • Support for adaptive sync feature
  • Support for High Dynamic Range (HDR) metadata
  • transport using secondary stream data packet

  • Auxiliary channel for 2-way communication (link and device management)
  • Hot plug detect (HPD)
  • Sink announces its presence
  • Sink requests the source’s attention
  • 8B/10B Channel Coding in SST mode supports the High-bandwidth Digital Content Protection (HDCP) feature for Intel Arria 10 and Intel Stratix 10 devices

    Typical Application

  • Interfaces within a PC or monitor
  • External display connections, including interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display

    Device Family Support

  • Intel Agilex™ (F-tile), Intel Stratix 10 (H-tile and L-tile), Intel Arria 10, Intel Cyclone 10 GX, Arria V, Cyclone V, and Stratix V FPGA devices.

    Design Tools

  • IP Catalog in the Intel Quartus Prime software for IP design instantiation and compilation
  • Timing Analyzer in the Intel Quartus Prime software for timing analysis
  • ModelSim* - Intel FPGA Edition, NCSim, VCS*/VCS MX, and Xcelium* Parallel software for design simulation
Device Family

Dual Symbol

(20 Bit Mode)

Quad Symbol

(40 Bit Mode)

FPGA Fabric Speed Grade

Intel Agilex (F-tile)

RBR, HBR, HBR2

RBR, HBR, HBR2, HBR3

1, 2, 3*

Intel Stratix 10 (H-tile)

RBR, HBR, HBR2

RBR, HBR, HBR2, HBR3, UHBR10

1, 2, 3*

Intel Stratix 10 (L-tile)

RBR, HBR, HBR2

RBR, HBR, HBR2, HBR3

1, 2, 3*

Intel Arria 10

RBR, HBR, HBR2

RBR, HBR, HBR2, HBR3

1, 2

Intel Cyclone® 10 GX

RBR, HBR, HBR2

RBR, HBR, HBR2, HBR3

5, 6

Stratix® V

RBR, HBR, HBR2

RBR, HBR, HBR2

1, 2, 3

Arria® V GX/GT/GS

RBR, HBR

RBR, HBR, HBR2

3, 4, 5

Arria® V GZ

RBR, HBR, HBR2

RBR, HBR, HBR2

Any supported speed grade

Cyclone® V

RBR, HBR

RBR, HBR

Any supported speed grade

Device

Streams

Direction

Symbol per

Clock

ALMs

Logic Registers

Primary

Logic Registers

Secondary

Memory Bits

Memory

M10K or M20K

Intel® Agilex™

SST

RX

Quad

7040

11781

-

18368

18

SST

TX

Quad

7600

10149

-

26576

29

Intel® Stratix® 10

SST (Single Stream)

RX

Dual

5,200

7,700

640

16,256

11

SST (Single Stream)

RX

Quad

7,100

9,500

880

18,816

14

SST (Single Stream)

TX

Dual

5,100

7,100

420

12,176

15

SST (Single Stream)

TX

Quad

7,100

9,200

550

22,688

29

Intel® Arria® 10

SST (Single Stream)

RX

Dual

4,200

6,900

1,200

16,256

11

SST (Single Stream)

RX

Quad

6,000

8,800

1,600

18,816

14

SST (Single Stream)

TX

Dual

4,700

6,300

1,000

6,728

6

SST (Single Stream)

TX

Quad

6,700

8,400

1,200

16,520

13

MST

RX

Quad

20,100

24,400

4,500

58,368

32

(4 Streams)

TX

Quad

26,400

29,000

4,300

21,728

34

Intel® Cyclone® 10 GX

SST (Single Stream)

RX

Dual

4,200

7,000

1,200

16,256

11

SST (Single Stream)

RX

Quad

6,000

8,800

1,600

18,816

14

SST (Single Stream)

TX

Dual

4,600

6,200

1,000

10,568

8

SST (Single Stream)

TX

Quad

6,800

8,400

1,200

17,096

13

MST

RX

Dual

22,000

24,400

4,400

58,368

32

(4 Streams)

TX

Quad

26,500

29,000

4,400

36,576

32

Device

Streams

Direction

Symbol per

Clock

ALMs

Logic Registers

Primary

Logic Registers

Secondary

Memory 

Bits

Memory

M10K or M20K

Intel® Stratix® 10

MST (1 Stream)

RX

-

21,500

38,000

-

244,352

74

MST (1 Stream)

TX

-

32,500

43,000

-

265,232

154

MST (4 Streams)

RX

-

48,000

70,751

-

357,632

164

MST (4 Streams)

TX

-

104,000

125,478

-

535,808

572

Device

HDCP IP

Support HDCP Key Management

Symbols per Clock

ALMs

Combinatorial ALUTs

Logic Registers

Memory M20K

DSP

Intel® Stratix® 10

HDCP 2.3 TX

0

Dual

7,723

11,555

13,685

10

3

HDCP 2.3 TX

0

Quad

10,767

17,154

17,842

10

3

HDCP 2.3 TX

1

Dual

8,232

12,376

14,123

12

3

HDCP 2.3 TX

1

Quad

11,082

17,741

18,125

12

3

HDCP 2.3 RX

0

Dual

8,431

12,626

14,647

11

3

HDCP 2.3 RX

0

Quad

11,304

18,071

18,586

11

3

HDCP 2.3 RX

1

Dual

8,796

13,174

14,707

13

3

HDCP 2.3 RX

1

Quad

11,690

18,658

18,847

13

3

HDCP 1.3 TX

0

Dual

3,154

4,108

5,181

2

0

HDCP 1.3 TX

0

Quad

4,794

6,194

7,640

2

0

HDCP 1.3 TX

1

Dual

3,614

4,894

5,916

4

0

HDCP 1.3 TX

1

Quad

5,169

6,979

6,791

4

0

HDCP 1.3 RX

0

Dual

2,602

3,355

4,245

3

0

HDCP 1.3 RX

0

Quad

4,229

5,428

6,452

3

0

HDCP 1.3 RX

1

Dual

3,045

4,022

4,904

5

0

HDCP 1.3 RX

1

Quad

4,656

6,173

5,773

5

0

Intel® Arria® 10

HDCP 2.3 TX

0

Dual

6,752

10,724

13,138

10

3

HDCP 2.3 TX

0

Quad

9,934

16,760

16,716

10

3

HDCP 2.3 TX

1

Dual

7,165

11,350

13,615

12

3

HDCP 2.3 TX

1

Quad

10,374

17,364

17,561

12

3

HDCP 2.3 RX

0

Dual

7,395

11,721

13,775

11

3

HDCP 2.3 RX

0

Quad

10,547

17,674

17,335

11

3

HDCP 2.3 RX

1

Dual

7,785

12,420

14,213

13

3

HDCP 2.3 RX

1

Quad

10,972

18,424

18,167

13

3

HDCP 1.3 TX

0

Dual

2,505

3,826

5,336

2

0

HDCP 1.3 TX

0

Quad

3,724

5,648

5,882

2

0

HDCP 1.3 TX

1

Dual

2,849

4,429

5,846

4

0

HDCP 1.3 TX

1

Quad

4,142

6,335

6,635

4

0

HDCP 1.3 RX

0

Dual

1,995

2,879

4,248

3

0

HDCP 1.3 RX

0

Quad

3,270

4,810

4,851

3

0

HDCP 1.3 RX

1

Dual

2,382

3,549

4,821

5

0

HDCP 1.3 RX

1

Quad

3,677

5,472

5,604

5

0

Device Design Example Designation Data Rate Channel Mode Loopback Type

Intel Agilex1

DisplayPort SST parallel loopback without PCR

DisplayPort SST

HBR3

Simplex

Parallel without PCR

Intel Stratix 10

DisplayPort SST parallel loopback with PCR (with and without HDCP)

DisplayPort SST

HBR3, HBR2, HBR, and RBR

Simplex

Parallel with PCR

DisplayPort SST parallel loopback without PCR

DisplayPort SST

UHBR10 (Stratix 10 H-tile), HBR3, HBR2, HBR, and RBR

Simplex

Parallel without PCR

Intel Arria 10

DisplayPort SST parallel loopback with PCR (with and without HDCP)

DisplayPort SST

HBR3, HBR2, HBR, and RBR

Simplex

Parallel with PCR

DisplayPort SST parallel loopback without PCR

DisplayPort SST

HBR3, HBR2, HBR, and RBR

Simplex

Parallel without PCR

DisplayPort MST parallel loopback with PCR

DisplayPort MST

HBR3, HBR2, HBR, and RBR

Simplex

Parallel with PCR

DisplayPort MST parallel loopback without PCR

DisplayPort MST

HBR3, HBR2, HBR, and RBR

Simplex

Parallel without PCR

DisplayPort SST TX-only

DisplayPort SST

HBR3, HBR2, HBR, and RBR

Simplex

-

DisplayPort SST RX-only

DisplayPort SST

HBR3, HBR2, HBR, and RBR

Simplex

-

Intel Cyclone 10 GX

DisplayPort SST parallel loopback with PCR

DisplayPort SST

HBR3, HBR2, HBR,and RBR

Simplex

Parallel with PCR

DisplayPort SST parallel loopback with PCR

DisplayPort SST

HBR3, HBR2, HBR, and RBR

Simplex

Parallel without PCR

DisplayPort MST parallel loopback with PCR

DisplayPort MST

HBR3, HBR2, HBR, and RBR

Simplex

Parallel with PCR

DisplayPort MST parallel loopback without PCR

DisplayPort MST

HBR3, HBR2, HBR, and RBR

Simplex

Parallel without PCR

Bitec FMC Daughtercard Revision

Supported Data Rate

Revision 8

RBR(1.62 Gbps), HBR(2.7 Gbps), HBR2(5.4 Gbps), HBR3(8.1 Gbps), UHBR10 (10 Gbps)

Revision 11

RBR(1.62 Gbps), HBR(2.7 Gbps), HBR2(2.7 Gbps), HBR3(8.1 Gbps)

Device

Device Part Number

Link to Pin Assignment Guide

Intel Stratix 10 Device

1SG280HU1F50E2VGS1

Intel Stratix 10 FPGA Design Example User Guide

Intel Arria 10 Device

10AX115S2F45I1SG

Intel Arria 10 FPGA Design Example User Guide

Intel Cyclone 10 GX Device

10CX220YF780E5G

Intel Cyclone 10 GX FPGA Design Example User Guide