How do I generate the Intel Quartus DisplayPort design example?
For Intel Agilex® 7, Intel Stratix, Intel Arria 10, and Intel Cyclone 10 GX devices, use the DisplayPort Intel FPGA parameter editor in the Intel Quartus Prime Pro Edition software to generate the design example.
- Click Tools > IP Catalog, and select target device family.
- In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
- Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named ip.
- You may select a specific FPGA device in the Device field, or keep the default Intel Quartus Prime software device selection.
- Click OK. The parameter editor appears.
- Configure the desired parameters for both TX and RX.
- On the Design Example tab, select the design example that fits your criteria.
- Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
- For Target Development Kit, select the available Intel FPGA development kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit.
- Click Generate Example Design.
Similarly, the links below provides step-by-step instruction to generate
DisplayPort design example from the Intel Quartus Prime software:
How do I compile and test my design?
For Intel Agilex 7 and 10-series devices, the steps to compile and test your DisplayPort design can be found in the following DisplayPort Design
Compiling and Testing the Design:
How can I perform DisplayPort functional simulation?
For Intel Agilex 7, Intel Stratix, Intel Arria 10, and Intel Cyclone 10 GX devices, below are the steps to generate DisplayPort functional simulation:
Enable the simulation option in the DisplayPort Parameter Editor and generate DisplayPort design example.
Where do I find information on the Clock Recovery Core?
The Intel Agilex 7, Intel Stratix, Intel Arria 10, and Intel Cyclone 10 GX DisplayPort design example uses Pixel Clock Recovery IP.
Clock Recovery Core information:
Where do I find information on the DisplayPort Link Training flow?
Before the source device can send video data to sink device, a Link Training process has to be completed between source-sink.
DisplayPort Link Training Flow:
Where do I find information on the DisplayPort API reference and DPCD information?
The following resources will provide instructions for the DisplayPort application programming interface (API) reference and DPCD: