Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design
- The reference design receives video data (up to a resolution of 3840 pixels × 2160 lines) over the DisplayPort RX link.
- The design then converts the received video to Avalon Streaming (Avalon-ST) image stream and stores into the external memory.
- The design mixes the buffered image with a 3840 × 2160 color bar background and sends the combined image to the DisplayPort Source.
- The DisplayPort Source transmits the combined image to a DisplayPort capable monitor over the DisplayPort TX link.
- The DisplayPort interface supports dynamic scaling between 1, 2 and 4 lanes:
- Reduced Bit Rate (RBR) @ 1.62 Gbps/lane
- High Bit Rate (HBR) @ 2.7 Gbps/lane
- High Bit Rate 2 (HBR2) @ 5.4 Gbps/lane
The TX and RX physical layer (PHY) are independent of each other although they are placed at the same transceiver channels; the DisplayPort Sink may run at 1 lane @ 2.7 Gbps while the DisplayPort Source runs at 4 lanes @ 5.4 Gbps concurrently. There is no audio or secondary stream being retransmitted in this reference design.
This reference design is implemented using Intel's Qsys integration tool and standalone HDL modules.
Did you find the information on this page useful?