AN 793: Intel® Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

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ID 683020
Date 6/13/2017
Public

Reference Design Components

The reference design consists of Qsys, PHY, and Clock subsystems.
Table 1.  Reference Design ComponentsThe table lists the major components in the reference design.
System Components
Qsys subsystem DisplayPort Source and Sink cores
Video and Image Processing IP cores
  • Clocked Video Input II (CVI)
  • Clocked Video Output II (CVO)
  • Frame Buffer II
  • Mixer II
Nios II processor
DDR4 External Memory Interface
Avalon Memory-Mapped (Avalon-MM) FIFO Memory
JTAG to Avalon-MM master bridge
PHY subsystem Simplex TX and RX Native PHY
TX fPLL
Intel® Transceiver PHY Reset Controller
TX and RX Bitec reconfiguration module
Transceiver reconfiguration arbiter
Clock subsystem IO PLL for video data path
Level Two Title