DisplayPort IP Core
The reference design uses specific DisplayPort IP core parameter settings.
| Parameter | Value | Notes | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Maximum video input color depth (TX) / Maximum video output color depth (RX) |
10 bpc |
This reference design supports GPU and monitor up to a maximum of 10 bit-per-color depth. |
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| Maximum link rate |
5.4 Gbps |
The bandwidth requirement for 4Kp60, 10 bpc video stream through serial link: Active video resolution = 3840 × 2160 pixels/frame Total resolution (including reduced blanking) = 4000 × 2222 pixels/frame Refresh rate = 60 Hz or 60 frames per second Bits per pixel = 10 bpc × 3 colors = 30 bits per pixel Total bandwidth = (4000 × 2222) pixel/frame × 60 frame/s × 30 bits/pixel = 15.9984 Gbits/s With 8b/10b encoding scheme, the actual bandwidth required = 15.9984 × 10/8 = 19.998 Gbps With 4 lanes at 5.4 Gbps, the aggregated bandwidth of 21.6 Gbps is sufficient to support the 4K video stream at 60 Hz refresh rate. |
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| Maximum lane count |
4 |
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| Symbol output mode (Source) / Symbol input mode (Sink) |
Dual |
Symbol mode affects the transceiver parallel bus width and the DisplayPort IP core clock frequency. The DisplayPort IP core synchronizes with the transceiver parallel clock. The parallel clock frequency is link rate/transceiver parallel bus width.
The table below shows the frequency for HBR2 (5.4 Gbps).
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| Pixel input mode (Source)/ Pixel output mode (Sink) |
Quad |
Pixel mode affects the video clock frequency and video port width of the IP core.
For 4Kp60 video stream, the bandwidth requirement is 4000 × 2222 × 60 pixel/s = 533280000 pixels/s. Because of the high bandwidth requirement, the design requires dual or quad pixel mode for timing closure.
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