AN 793: Intel® Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

ID 683020
Date 6/13/2017


The DisplayPort main link uses the Native PHY IP core for serial communication between the GPU and monitor.

The reference design uses separate simplex TX and RX PHY blocks because the TX and RX channels may run at different data rates based on the link training results.

Table 6.  Native PHY Parameter Settings
Parameter Value Corresponding DisplayPort Source/Sink Parameters
Number of data channels 4 Maximum lane count = 4
Data rate (Mbps) 5,400 TX/RX maximum link rate = 5.4 Gbps
Standard PCS/PMA interface width 20 Symbol input/output mode = Dual
TX/RX byte serializer mode Disabled
The design uses two Intel® transceiver PHY reset controllers to control the TX and RX PHY blocks independently.
Note: The 70 µs delay is not applied to the transceiver PHY reset controllers because the delay is too long for the DisplayPort Source and Sink cores to complete the link training. Instead, the design uses the acknowledgment model.

The Bitec reconfiguration management module controls the reset input of the PHY reset controllers, and manages the dynamic reconfiguration of the TX PHY, RX PHY and TX PLL blocks for data rate switch and PMA analog settings (TX VOD and pre-emphasis). To fulfill the simplex TX and RX PHY channel merging requirement, a transceiver arbiter is inserted in between the Bitec reconfiguration module Avalon-MM master and the PHY reconfiguration Avalon-MM slave interface.