|Signal||Description||Pin Number||I/O Standard||Usage|
External 100 MHz clock from X3 programmable oscillator on the FPGA development kit.
External 135 MHz clock from Bitec FMC daughter card. The oscillator is not programmable.
External 133 MHz clock from U26 programmable oscillator on the FPGA development kit.
|F34/F35||LVDS||DDR4 external memory interface input reference clock|
Generated 133.33 MHz clock from video PLL.
|–||DisplayPort Source–Clocked Video Output interface|
Generated 160 MHz clock from video PLL.
Generated 16MHz clock from video PLL
Derived 50MHz clock from refclk1
|–||–||DisplayPort Sink and Source calibration. This clock must be synchronous to the clock used for the transceiver reconfiguration block (100 MHz)|
The 133.33 MHz clock output from the video PLL drives the DisplayPort Source and Clocked Video Output interface. The CVT-RB specification states that the 133.33 MHz should be derived from the reduced blanking period of the 4K video output stream.
|H Active × V Active||H Total||H Blank||V Total||V Blank||Pixel Frequency|
Did you find the information on this page useful?