AN 793: Intel® Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

ID 683020
Date 6/13/2017

External Memory Interface

The Frame Buffer II IP core uses the external SDRAM to triple-buffer video frames and handle mismatch in RX and TX video data rates.

The IP core writes to the memory to store input pixels and reads from the memory to retrieve video frames and transmit them. The Arria® 10 FPGA Development Kit has a HiLo connector for the DDR4 module. The DDR4 module is part of the development kit. The module has x72 @ 1200 MHz interface.

The Arria® 10 GX FPGA Development Kit with DDR4 HiLo preset applies to the External Memory Interface instance, except for DQ width set to 64. The Frame Buffer II IP core supports up to a DQ width of x64.