AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

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ID 683799
Date 7/02/2021
Public
Document Table of Contents
Document Table of Contents
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the RX-only Design 1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design
1.4. Quick Start Guide
1.4.1. Hardware and Software Requirements 1.4.2. Directory Structure 1.4.3. Compiling the Design 1.4.4. Running the Design on Hardware 1.4.5. Design Debug Features
1.4.3. Compiling the Design
1.4.3.1. Regenerating and Downloading ELF File
1.4.5. Design Debug Features
1.4.5.1. Main Stream Attribute (MSA) Information 1.4.5.2. Auxiliary Channel Traffic Monitor 1.4.5.3. Signal Tap Logic Analyzer 1.4.5.4. Onboard User LED Functions
1.5. Creating the RX-only Design
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Making a Direct Connection to the RX Transceiver Block 1.5.4. Selecting the Bitec FMC Daughter Card Revision 1.5.5. Modifying the Software
1.5.2. Removing Irrelevant Blocks
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort 8K RX-only Design

1.4.5.2. Auxiliary Channel Traffic Monitor

This debug feature enables you to check the auxiliary channel transaction.
This feature is also a part of the DisplayPort RX-only design example. To display the auxiliary channel transaction on the Nios® II terminal, set the BITEC_AUX_DEBUG flag in the config.h file in the project folder to 1. 
#define BITEC_AUX_DEBUG 1 // Set to 1 to enable AUX CH traffic monitoring
Rebuild the Nios II software and download the ELF image into the FPGA.
Note: This design also has the Enable AUX Debug Stream parameter, in the DisplayPort IP parameter editor, turned on to enable the AUX channel traffic monitor feature.
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