1.5.3. Making a Direct Connection to the RX Transceiver Block
- Before you make the connection, in the Platform Designer turn on the Share Reconfiguration Interface parameter in the Transceiver Native PHY block to allow for single Avalon® memory-mapped slave interface for dynamic reconfiguration of all channels.
- Update the width of the transceiver signals as shown below in the design top-level and the rx_phy_top.v files.
Table 12. RX Transceiver Signals Signal Direction Width (Bit) gxb_rx_rcfg_write Input 1 gxb_rx_rcfg_read Input 1 gxb_rx_rcfg_address Input 12 gxb_rx_rcfg_writedata Input 32 gxb_rx_rcfg_readdata Output 32 gxb_rx_rcfg_waitrequest Output 1 gxb_rx_rcfg_cal_busy Output 1
- Make a direct connection from the RX Reconfiguration Management block to the RX Transceiver Native PHY block in the rx_phy_top.v file as shown in the diagram below.
Figure 7. Bitec Reconfig and RX Transceiver Block Connection
- Remove the following Transceiver Reconfig Group assignments from the Intel® Quartus® Prime Settings File (.qsf).
- - set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to fmca_dp_m2c_p -entity a10_dp_demo
- - set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to fmca_dp_m2c_p -entity a10_dp_demo
- - set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to fmca_dp_m2c_p -entity a10_dp_demo
- - set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to fmca_dp_m2c_p -entity a10_dp_demo
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