AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

ID 683799
Date 7/02/2021

1.2. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel® FPGA IP design example.
Table 4.  Clocking Scheme Signals
Clock Signal Name in Design Description
RX PLL Refclock rx_cdr_refclk

135 MHz transceiver clock data recovery (CDR) reference clock that is divisible by the transceiver for all DisplayPort data rates (1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps).

Note: The reference clock source of the RX refclock is located at the HSSI refclk pin.
RX Transceiver Clockout gxb_rx_clkout

RX clock recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.

Data Rate Symbols per Clock Frequency (MHz)

RBR (1.62 Gbps)

2 (dual)

4 (quad) 40.5

HBR (2.7 Gbps)

2 (dual) 135
4 (quad) 67.5

HBR2 (5.4 Gbps)

2 (dual) 270
4 (quad) 135
HBR3 (8.1 Gbps) 4 (quad) 202.5
Management Clock


A free running 100 MHz clock for both Avalon® memory-mapped interfaces for reconfiguration and PHY reset controller for transceiver reset sequence.

Component Required Frequency (MHz)
Avalon® memory-mapped reconfiguration 100 – 125
Transceiver PHY reset controller 1 – 500
16 MHz Clock dp_rx_clk_16_in_clk

16 MHz clock used to encode and decode auxiliary channel in the DisplayPort Intel® FPGA IP sink core.

Calibration Clock


A 50 MHz calibration clock input that must be synchronous to the Transceiver Reconfiguration module's clock. This clock is used in the DisplayPort Intel® FPGA IP 's reconfiguration logic.

RX Video Clock dp_rx_dp_sink_rx_vid_clk

A 300 MHz video clock for DisplayPort sink to clock video data stream.

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