AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

Download PDF
ID 683799
Date 7/02/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1. Intel® Arria® 10 DisplayPort 8K RX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the RX-only Design 1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Directory Structure 1.4.3. Compiling the Design 1.4.4. Running the Design on Hardware 1.4.5. Design Debug Features
1.4.3. Compiling the Design x
1.4.3.1. Regenerating and Downloading ELF File
1.4.5. Design Debug Features x
1.4.5.1. Main Stream Attribute (MSA) Information 1.4.5.2. Auxiliary Channel Traffic Monitor 1.4.5.3. Signal Tap Logic Analyzer 1.4.5.4. Onboard User LED Functions
1.5. Creating the RX-only Design x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Making a Direct Connection to the RX Transceiver Block 1.5.4. Selecting the Bitec FMC Daughter Card Revision 1.5.5. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort 8K RX-only Design

1.4.2. Directory Structure

The directory structure lists the folders and files needed for the design.
Table 9.   Intel® Arria® 10 DisplayPort 8K RX-only Design Directory StructureThe 8K DisplayPort RX-only design file (A10_DP_RX_FMC_PRO.par) has the Additional_Files.zip file that contains the master image and other software files. Unzip the Additional_Files.zip file and restructure the folders accordingly based on the table below.
Folder File/Folder
Main top.qpf
top.qsf
rtl/
script/ (extracted from Additional_Files.zip)
software/ (extracted from Additional_Files.zip)
Additional_Files/ (extracted from Additional_Files.zip)
ReadMe.txt
DP_RX.stp
rtl/ a10_dp_demo.v
reset_gen.sv
bitec_reconfig_alt_a10.v
video_pll_a10.ip
reset_sync.sv
example.sdc
rtl/core/ dp_rx.qsys
dp_core.qsys
<Platform Designer (Standard)-generated files and folder>
rtl/rx_phy/ gxb_rx.ip
gxb_rx_reset.ip
rx_phy_top.v
<Platform Designer (Standard)-generated files and folder>
rtl/video_pll_a10/ video_pll_a10.qip
<Platform Designer (Standard)-generated files and folder>
script build_ip.tcl
build_sw.sh
software/ <Other software files and folder>
software/dp_demo/ dp_demo.elf
main.c
config.h
rx_utils.c
debug.c
<Other software files and folder>
software/dp_demo_bsp/ alt_sys_init.c
linker.h
system.h
<Other software files and folder>
software/dp_demo_bsp/ <Other software files and folder>
software/dp_demo_bsp/ <Other software files and folder>
software/dp_demo_bsp/ <Other software files and folder>
Additional_Files/Master_Image/Rev_11 a10_dp_demo.sof
dp_demo.elf
Level Two Title