AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

ID 683799
Date 7/02/2021
Public

1.5.1. Generating the Design

Before you make the modifications, first you need to generate the DisplayPort SST Parallel Loopback design example in the Intel® Quartus® Prime Pro Edition software.
  1. Instantiate the DisplayPort Intel® FPGA IP and specify the parameters.
    Table 11.  DisplayPort SST Parallel Loopback Parameters
    Parameters Value Description
    Maximum video output color depth (TX) 16 bpc This design supports GPU and monitors up to a maximum of 16 bit-per-color depth. However, the design depends highly on the GPU's capability to transmit the color depth.
    Note: Intel source devices are capable of transmitting 8Kp30 with 8 bpc settings.
    Maximum link rate 8.1 Gbps The bandwidth requirement for 8Kp30 and 8 bpc video stream through serial link:
    • Active video resolution = 7680 × 4320 pixels per frame
    • Total resolution (including reduced blanking) = 7760 × 4381 pixels per frame
    • Refresh rate = 30 Hz or 30 frames per second
    • Bits per pixel = 8 bpc × 3 colors = 24 bits per pixel
    • Total bandwidth = (7760 × 4381) pixels per frame × 30 frames per second × 24 bits per pixel = 24.477 Gbps
    With 8B/10B encoding scheme, the actual bandwidth required = 24.477 Gbps × 10/8 = 30.59 Gbps.

    With 4 lanes at 8.1 Gbps, the aggregated bandwidth of 32.4 Gbps is sufficient to support the 8K video stream at 30 Hz refresh rate.

    Maximum lane count 4
    Symbol output mode (Source) Quad

    Symbol mode affects the transceiver parallel bus width and the DisplayPort IP clock frequency. The DisplayPort IP synchronizes with the transceiver parallel clock. The parallel clock frequency is link rate/transceiver parallel bus width.

    Frequency for HBR3 (8.1 Gbps) is 8100/40 or 202.5 MHz for quad (40 bits) mode.
    Symbol input mode (Sink)
    Pixel input mode (Source) Quad

    Pixel mode affects the video clock frequency and video port width of the IP core.

    For 8Kp30 video stream, the bandwidth requirement is 7760 (H-total) × 4381 (V-total) × 30 frames per second = 1019896800 pixels per second. Because of the high bandwidth requirement, the design requires quad pixel mode for timing closure.

    • Single (1 pixel/clock): 1019.89 MHz
    • Dual (2 pixels/clock) 509.95 MHz
    • Quad (4 pixels/clock) 254.97 MHz
    Note: This design uses 300 MHz for the video clock generated from PLL.
    Pixel output mode (Sink)
    Support analog reconfiguration On Enable analog reconfiguration interface. Used to reconfigure vod and pre-emphasis value.
    Enable AUX debug stream On Enable AUX source traffic output to the Avalon® streaming port
    DisplayPort SST Parallel Loopback With PCR On Enable Pixel Clock Recovery in the design.
    Note: The table above is an example of IP setting. However, it is recommended to generate base example design with required IP setting (BPC, symbol per clock, pixel per clock, number of channels, link rate) and then proceed with the design modification. Changing the IP settings at the later stage may cause design conflict if not done properly.
  2. Click Generate Example Design with Intel® Arria® 10 GX FPGA Development Kit as a target board.

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